From: "Marek Behún" <marek.behun@nic.cz>
To: linux-pci@vger.kernel.org
Cc: "Jason Cooper" <jason@lakedaemon.net>,
"Andrew Lunn" <andrew@lunn.ch>,
"Gregory Clement" <gregory.clement@bootlin.com>,
"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Andrew Murray" <amurray@thegoodpenguin.co.uk>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Remi Pommarel" <repk@triplefau.lt>,
"Tomasz Maciej Nowak" <tmn505@gmail.com>,
Xogium <contact@xogium.me>, "Pali Rohár" <pali@kernel.org>
Subject: [PATCH v2 2/9] PCI: aardvark: don't write to read-only register
Date: Tue, 21 Apr 2020 13:16:54 +0200 [thread overview]
Message-ID: <20200421111701.17088-3-marek.behun@nic.cz> (raw)
In-Reply-To: <20200421111701.17088-1-marek.behun@nic.cz>
From: Pali Rohár <pali@kernel.org>
Trying to change Link Status register does not have any effect as this
is a read-only register. Trying to overwrite bits for Negotiated Link
Width does not make sense.
In future proper change of link width can be done via Lane Count Select
bits in PCIe Control 0 register.
Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link
Control register is wrong. There should be at least some detection if
endpoint supports L0s as isn't mandatory.
Moreover ASPM Control bits in Link Control register are controlled by
pcie/aspm.c code which sets it according to system ASPM settings,
immediately after aardvark driver probes. So setting these bits by
aardvark driver has no long running effect.
Remove code which touches ASPM L0s bits from this driver and let
kernel's ASPM implementation to set ASPM state properly.
Some users are reporting issues that this code is problematic for some
Intel wifi cards and removing it fixes them, see e.g.:
https://bugzilla.kernel.org/show_bug.cgi?id=196339
If problems with Intel wifi cards occur even after this commit, then
pcie/aspm.c code could be modified / hooked to not enable ASPM L0s state
for affected problematic cards.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index b59198a102d0..551d98174613 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -356,10 +356,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_pcie_wait_for_link(pcie);
- reg = PCIE_CORE_LINK_L0S_ENTRY |
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
- advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
-
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
PCIE_CORE_CMD_IO_ACCESS_EN |
--
2.24.1
next prev parent reply other threads:[~2020-04-21 11:17 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-21 11:16 [PATCH v2 0/9] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Marek Behún
2020-04-21 11:16 ` [PATCH v2 1/9] PCI: aardvark: train link immediately after enabling training Marek Behún
2020-04-21 11:16 ` Marek Behún [this message]
2020-04-23 17:27 ` [PATCH v2 2/9] PCI: aardvark: don't write to read-only register Bjorn Helgaas
2020-04-23 17:51 ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 3/9] PCI: aardvark: improve link training Marek Behún
2020-04-23 18:39 ` Bjorn Helgaas
2020-04-23 18:56 ` Pali Rohár
2020-04-24 12:49 ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 4/9] PCI: aardvark: issue PERST via GPIO Marek Behún
2020-04-23 18:41 ` Bjorn Helgaas
2020-04-23 19:02 ` Pali Rohár
2020-04-23 22:17 ` Bjorn Helgaas
2020-04-23 22:23 ` Pali Rohár
2020-04-23 22:40 ` Bjorn Helgaas
2020-04-24 8:13 ` Pali Rohár
2020-04-24 9:25 ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 5/9] PCI: aardvark: add FIXME comment for PCIE_CORE_CMD_STATUS_REG access Marek Behún
2020-04-23 18:44 ` Bjorn Helgaas
2020-04-23 19:06 ` Pali Rohár
2020-04-21 11:16 ` [PATCH v2 6/9] PCI: aardvark: add PHY support Marek Behún
2020-04-21 11:16 ` [PATCH v2 7/9] dt-bindings: PCI: aardvark: describe new properties Marek Behún
2020-05-11 18:24 ` Rob Herring
2020-04-21 11:17 ` [PATCH v2 8/9] arm64: dts: marvell: armada-37xx: set pcie_reset_pin to gpio function Marek Behún
2020-04-21 11:17 ` [PATCH v2 9/9] arm64: dts: marvell: armada-37xx: move PCIe comphy handle property Marek Behún
2020-04-21 11:42 ` [PATCH v2 0/9] PCI: aardvark: Fix support for Turris MOX and Compex wifi cards Pali Rohár
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200421111701.17088-3-marek.behun@nic.cz \
--to=marek.behun@nic.cz \
--cc=amurray@thegoodpenguin.co.uk \
--cc=andrew@lunn.ch \
--cc=bhelgaas@google.com \
--cc=contact@xogium.me \
--cc=gregory.clement@bootlin.com \
--cc=jason@lakedaemon.net \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=pali@kernel.org \
--cc=repk@triplefau.lt \
--cc=sebastian.hesselbarth@gmail.com \
--cc=thomas.petazzoni@bootlin.com \
--cc=tmn505@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).