From: Jason Gunthorpe <jgg@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
"Marc Zyngier" <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>, <linux-pci@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] PCI: tegra: Convert to MSI domains
Date: Fri, 4 Sep 2020 08:45:01 -0300 [thread overview]
Message-ID: <20200904114501.GO1152540@nvidia.com> (raw)
In-Reply-To: <20200904105613.444945-1-thierry.reding@gmail.com>
On Fri, Sep 04, 2020 at 12:56:13PM +0200, Thierry Reding wrote:
> +static void tegra_msi_irq_mask(struct irq_data *d)
> +{
> + struct tegra_msi *msi = irq_data_get_irq_chip_data(d);
> + struct tegra_pcie *pcie = msi_to_pcie(msi);
> + unsigned int index = d->hwirq / 32;
> + u32 value;
> +
> + value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
> + value &= ~BIT(d->hwirq % 32);
> + afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
> +}
Do these need a flushing write? The Mask operation should be synchronous?
Thanks,
Jason
next prev parent reply other threads:[~2020-09-04 11:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-04 10:56 [PATCH] PCI: tegra: Convert to MSI domains Thierry Reding
2020-09-04 11:45 ` Jason Gunthorpe [this message]
2020-09-04 12:28 ` Thierry Reding
2020-09-04 12:30 ` Jason Gunthorpe
2020-09-04 15:48 ` Marc Zyngier
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