From: Krzysztof Kozlowski <krzk@kernel.org>
To: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung <jh80.chung@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards
Date: Mon, 19 Oct 2020 12:31:00 +0200 [thread overview]
Message-ID: <20201019103100.GA53305@kozik-lap> (raw)
In-Reply-To: <20201019094715.15343-7-m.szyprowski@samsung.com>
On Mon, Oct 19, 2020 at 11:47:15AM +0200, Marek Szyprowski wrote:
> From: Jaehoon Chung <jh80.chung@samsung.com>
>
> Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
> WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> [mszyprow: rewrote commit message, reworked board/generic dts/dtsi split]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
> .../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++-
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 +++++++++++++++++++
> 3 files changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> index 9df7c65593a1..32a6518517e5 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> @@ -329,7 +329,7 @@
> };
>
> pcie_bus: pcie_bus {
> - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
> + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6";
> samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> };
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 829fea23d4ab..ef45ef86c48d 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -969,6 +969,25 @@
> bus-width = <4>;
> };
>
> +&pcie {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_bus &pcie_wlanen>;
> + vdd10-supply = <&ldo6_reg>;
> + vdd18-supply = <&ldo7_reg>;
> + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
> + <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
> + assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> + assigned-clock-rates = <0>, <100000000>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&pcie_phy {
> + status = "okay";
> +};
> +
> &ppmu_d0_general {
> status = "okay";
> events {
> @@ -1085,8 +1104,11 @@
> pinctrl-names = "default";
> pinctrl-0 = <&initial_ese>;
>
> + pcie_wlanen: pcie-wlanen {
> + PIN(INPUT, gpj2-0, UP, FAST_SR4);
> + };
> +
> initial_ese: initial-state {
> - PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
> PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
> PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
> };
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 8eb4576da8f3..be2d1753d1d1 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -1029,6 +1029,11 @@
> reg = <0x145f0000 0x1038>;
> };
>
> + syscon_fsys: syscon@156f0000 {
> + compatible = "syscon";
> + reg = <0x156f0000 0x1044>;
> + };
> +
> gsc_0: video-scaler@13c00000 {
> compatible = "samsung,exynos5433-gsc";
> reg = <0x13c00000 0x1000>;
> @@ -1830,6 +1835,37 @@
> status = "disabled";
> };
> };
> +
> + pcie_phy: pcie-phy@15680000 {
> + compatible = "samsung,exynos5433-pcie-phy";
> + reg = <0x15680000 0x1000>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + samsung,fsys-sysreg = <&syscon_fsys>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + pcie: pcie@15700000 {
> + compatible = "samsung,exynos5433-pcie";
> + reg = <0x156b0000 0x1000>, <0x15700000 0x1000>,
> + <0x0c000000 0x1000>;
dtc should complain here:
arch/arm64/boot/dts/exynos/exynos5433.dtsi:1848.23-1868.5: Warning (simple_bus_reg): /soc@0/pcie@15700000: simple-bus unit address format error, expected "156b0000"
> + reg-names = "elbi", "dbi", "config";
This does not match your own bindings:
pcie@15700000: reg-names:1: 'bdi' was expected
pcie@15700000: 'interrupt-names' is a required property
Best regards,
Krzysztof
prev parent reply other threads:[~2020-10-19 10:31 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20201019094737eucas1p283ea94186450c0756442624d95de627f@eucas1p2.samsung.com>
2020-10-19 9:47 ` [PATCH 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
[not found] ` <CGME20201019094738eucas1p29b377b561089cfc3eba1755d475125b9@eucas1p2.samsung.com>
2020-10-19 9:47 ` [PATCH 1/6] Documetation: dt-bindings: drop samsung,exynos5440-pcie binding Marek Szyprowski
2020-10-19 10:08 ` Krzysztof Kozlowski
2020-10-19 20:07 ` Rob Herring
[not found] ` <CGME20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d@eucas1p1.samsung.com>
2020-10-19 9:47 ` [PATCH 2/6] Documetation: dt-bindings: add the samsung,exynos-pcie binding Marek Szyprowski
2020-10-19 10:12 ` Krzysztof Kozlowski
2020-10-19 10:18 ` Krzysztof Kozlowski
2020-10-21 11:59 ` Marek Szyprowski
2020-10-21 12:12 ` Krzysztof Kozlowski
2020-10-19 10:28 ` Krzysztof Kozlowski
2020-10-19 13:38 ` Rob Herring
2020-10-21 12:05 ` Marek Szyprowski
[not found] ` <CGME20201019094739eucas1p17424b1224bf2a1a5b16c33deb4209166@eucas1p1.samsung.com>
2020-10-19 9:47 ` [PATCH 3/6] Documetation: dt-bindings: add the samsung,exynos-pcie-phy binding Marek Szyprowski
2020-10-19 10:14 ` Krzysztof Kozlowski
2020-10-19 20:09 ` Rob Herring
[not found] ` <CGME20201019094740eucas1p10ea264deb2cd185858d0dfdd9f6ed6fe@eucas1p1.samsung.com>
2020-10-19 9:47 ` [PATCH 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
2020-10-19 10:16 ` Krzysztof Kozlowski
[not found] ` <CGME20201019094740eucas1p2cd873b29bc19708f9a712d955cba62fe@eucas1p2.samsung.com>
2020-10-19 9:47 ` [PATCH 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-19 10:21 ` Krzysztof Kozlowski
[not found] ` <CGME20201019094741eucas1p1b4934cd5024a18804fcee921294acee0@eucas1p1.samsung.com>
2020-10-19 9:47 ` [PATCH 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Marek Szyprowski
2020-10-19 10:31 ` Krzysztof Kozlowski [this message]
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