From: Marek Szyprowski <m.szyprowski@samsung.com>
To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung <jh80.chung@samsung.com>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v2 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards
Date: Fri, 23 Oct 2020 09:57:44 +0200 [thread overview]
Message-ID: <20201023075744.26200-7-m.szyprowski@samsung.com> (raw)
In-Reply-To: <20201023075744.26200-1-m.szyprowski@samsung.com>
From: Jaehoon Chung <jh80.chung@samsung.com>
Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
[mszyprow: rewrote commit message, reworked board/generic dts/dtsi split]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
.../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
.../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++-
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 35 +++++++++++++++++++
3 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
index 9df7c65593a1..32a6518517e5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -329,7 +329,7 @@
};
pcie_bus: pcie_bus {
- samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
+ samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 829fea23d4ab..6e45a42be562 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -969,6 +969,25 @@
bus-width = <4>;
};
+&pcie {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+ vdd10-supply = <&ldo6_reg>;
+ vdd18-supply = <&ldo7_reg>;
+ assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
+ <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
+ assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>;
+ assigned-clock-rates = <0>, <100000000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
&ppmu_d0_general {
status = "okay";
events {
@@ -1085,8 +1104,11 @@
pinctrl-names = "default";
pinctrl-0 = <&initial_ese>;
+ pcie_wlanen: pcie-wlanen {
+ PIN(INPUT, gpj2-0, UP, FAST_SR4);
+ };
+
initial_ese: initial-state {
- PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 8eb4576da8f3..4d25b7d2486c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1029,6 +1029,11 @@
reg = <0x145f0000 0x1038>;
};
+ syscon_fsys: syscon@156f0000 {
+ compatible = "syscon";
+ reg = <0x156f0000 0x1044>;
+ };
+
gsc_0: video-scaler@13c00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
@@ -1830,6 +1835,36 @@
status = "disabled";
};
};
+
+ pcie_phy: pcie-phy@15680000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie: pcie@15700000 {
+ compatible = "samsung,exynos5433-pcie";
+ reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
+ <0x0c000000 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PCIE>,
+ <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+ clock-names = "pcie", "pcie_bus";
+ num-lanes = <1>;
+ bus-range = <0x00 0xff>;
+ phys = <&pcie_phy>;
+ ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
+ <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+ status = "disabled";
+ };
};
timer: timer {
--
2.17.1
prev parent reply other threads:[~2020-10-23 7:58 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20201023075754eucas1p2ee617893ba13493236814235c619bc56@eucas1p2.samsung.com>
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
[not found] ` <CGME20201023075754eucas1p2a4c9c5467f25a575bec34984fe6bb43b@eucas1p2.samsung.com>
2020-10-23 7:57 ` [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Marek Szyprowski
2020-10-24 2:59 ` Jingoo Han
[not found] ` <CGME20201023075755eucas1p290b7bc020e46b86fe5e7591877f87117@eucas1p2.samsung.com>
2020-10-23 7:57 ` [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
2020-10-23 9:26 ` Krzysztof Kozlowski
[not found] ` <CGME20201023075755eucas1p165641c7528ea987a2e1d9d28198c0e9e@eucas1p1.samsung.com>
2020-10-23 7:57 ` [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
2020-10-23 9:28 ` Krzysztof Kozlowski
[not found] ` <CGME20201023075756eucas1p2c27cc3e6372127d107e5b84c810ba98f@eucas1p2.samsung.com>
2020-10-23 7:57 ` [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
2020-10-24 3:00 ` Jingoo Han
2020-10-26 18:50 ` Rob Herring
2020-10-27 12:28 ` Marek Szyprowski
[not found] ` <CGME20201023075756eucas1p18765653e747842eef4b438aff32ef136@eucas1p1.samsung.com>
2020-10-23 7:57 ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-23 15:09 ` kernel test robot
2020-10-24 3:12 ` Jingoo Han
2020-10-26 2:49 ` Jaehoon Chung
2020-10-26 4:08 ` Jingoo Han
2020-10-26 19:14 ` Rob Herring
2020-10-27 12:04 ` Marek Szyprowski
2020-10-27 13:24 ` Marek Szyprowski
[not found] ` <CGME20201023075757eucas1p13e4e7f5177bd3f789ac0d2a8aa57c86e@eucas1p1.samsung.com>
2020-10-23 7:57 ` Marek Szyprowski [this message]
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