From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
To: bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
andriy.shevchenko@linux.intel.com, mgross@linux.intel.com,
lakshmi.bai.raja.subramanian@intel.com,
wan.ahmad.zainie.wan.mohamad@intel.com
Subject: [PATCH v2 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller
Date: Wed, 25 Nov 2020 18:11:51 +0800 [thread overview]
Message-ID: <20201125101152.5326-2-wan.ahmad.zainie.wan.mohamad@intel.com> (raw)
In-Reply-To: <20201125101152.5326-1-wan.ahmad.zainie.wan.mohamad@intel.com>
Document DT bindings for PCIe controller found on Intel Keem Bay SoC.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
.../bindings/pci/intel,keembay-pcie-ep.yaml | 68 +++++++++++++
.../bindings/pci/intel,keembay-pcie.yaml | 96 +++++++++++++++++++
2 files changed, 164 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
new file mode 100644
index 000000000000..8cf72b80cfb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Keem Bay PCIe controller endpoint mode
+
+maintainers:
+ - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+properties:
+ compatible:
+ const: intel,keembay-pcie-ep
+
+ reg:
+ maxItems: 5
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: atu
+ - const: addr_space
+ - const: apb
+
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ items:
+ - const: pcie
+ - const: pcie_ev
+ - const: pcie_err
+ - const: pcie_mem_access
+
+ num-lanes:
+ description: Number of lanes to use.
+ enum: [ 1, 2 ]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pcie-ep@37000000 {
+ compatible = "intel,keembay-pcie-ep";
+ reg = <0x37000000 0x00001000>,
+ <0x37100000 0x00001000>,
+ <0x37300000 0x00001000>,
+ <0x36000000 0x01000000>,
+ <0x37800000 0x00000200>;
+ reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
+ num-lanes = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
new file mode 100644
index 000000000000..d9c72783ab05
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Keem Bay PCIe controller root complex mode
+
+maintainers:
+ - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: intel,keembay-pcie
+
+ ranges:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: atu
+ - const: config
+ - const: apb
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: master
+ - const: aux
+
+ interrupts:
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: pcie
+ - const: pcie_ev
+ - const: pcie_err
+
+ num-lanes:
+ description: Number of lanes to use.
+ enum: [ 1, 2 ]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - ranges
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #define KEEM_BAY_A53_PCIE
+ #define KEEM_BAY_A53_AUX_PCIE
+ pcie@37000000 {
+ compatible = "intel,keembay-pcie";
+ reg = <0x37000000 0x00001000>,
+ <0x37300000 0x00001000>,
+ <0x36e00000 0x00200000>,
+ <0x37800000 0x00000200>;
+ reg-names = "dbi", "atu", "config", "apb";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "pcie_ev", "pcie_err";
+ clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
+ <&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
+ clock-names = "master", "aux";
+ reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
+ num-lanes = <2>;
+ };
--
2.17.1
next prev parent reply other threads:[~2020-11-25 10:13 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 10:11 [PATCH v2 0/2] PCI: keembay: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-11-25 10:11 ` Wan Ahmad Zainie [this message]
2020-11-25 10:11 ` [PATCH v2 2/2] " Wan Ahmad Zainie
2020-11-25 12:50 ` Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201125101152.5326-2-wan.ahmad.zainie.wan.mohamad@intel.com \
--to=wan.ahmad.zainie.wan.mohamad@intel.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=lakshmi.bai.raja.subramanian@intel.com \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mgross@linux.intel.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).