From: Simon Xue <xxm@rock-chips.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
Simon Xue <xxm@rock-chips.com>
Subject: [PATCH 2/3] dt-bindings: rockchip: Add DesignWare based PCIe controller
Date: Mon, 18 Jan 2021 17:17:38 +0800 [thread overview]
Message-ID: <20210118091739.247040-2-xxm@rock-chips.com> (raw)
In-Reply-To: <20210118091739.247040-1-xxm@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
---
.../bindings/pci/rockchip-dw-pcie.yaml | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
new file mode 100644
index 000000000000..fa664cfffb29
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe RC controller on Rockchip SoCs
+
+maintainers:
+ - Shawn Lin <shawn.lin@rock-chips.com>
+ - Simon Xue <xxm@rock-chips.com>
+
+# We need a select here so we don't match all nodes with 'snps,dw-pcie'
+select:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3568-pcie
+ required:
+ - compatible
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-pcie
+ - snps,dw-pcie
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AHB clock for PCIe master
+ - description: AHB clock for PCIe slave
+ - description: AHB clock for PCIe dbi
+ - description: APB clock for PCIe
+ - description: Auxiliary clock for PCIe
+
+ clock-names:
+ items:
+ - const: aclk_mst
+ - const: aclk_slv
+ - const: aclk_dbi
+ - const: pclk
+ - const: aux
+
+ resets:
+ items:
+ - description: PCIe pipe reset line
+
+ reset-names:
+ items:
+ - const: pipe
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - bus-range
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - msi-map
+ - num-lanes
+ - phys
+ - phy-names
+ - ranges
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie3x2: pcie@fe280000 {
+ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x20 0x2f>;
+ reg = <0x3 0xc0800000 0x0 0x400000>,
+ <0x0 0xfe280000 0x0 0x10000>;
+ reg-names = "pcie-dbi", "pcie-apb";
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ msi-map = <0x2000 &its 0x2000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000
+ 0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
+ 0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
+ reset-names = "pipe";
+ };
+
+...
--
2.25.1
next prev parent reply other threads:[~2021-01-18 20:08 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-18 9:17 [PATCH 1/3] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Simon Xue
2021-01-18 9:17 ` Simon Xue [this message]
2021-01-19 13:07 ` [PATCH 2/3] dt-bindings: rockchip: Add DesignWare based PCIe controller Johan Jonker
2021-01-19 13:14 ` Heiko Stübner
2021-01-19 15:11 ` Johan Jonker
2021-01-19 18:40 ` Robin Murphy
2021-01-20 14:16 ` Rob Herring
2021-01-20 14:54 ` Heiko Stübner
2021-01-20 16:20 ` Robin Murphy
2021-01-19 19:58 ` Robin Murphy
2021-01-20 10:06 ` xxm
2021-01-18 9:17 ` [PATCH 3/3] PCI: rockchip: add " Simon Xue
2021-01-19 20:28 ` Robin Murphy
2021-01-20 1:58 ` xxm
2021-01-19 19:47 ` [PATCH 1/3] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Robin Murphy
2021-01-20 1:53 ` xxm
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