From: Jianjun Wang <jianjun.wang@mediatek.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>, <maz@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Ryder Lee <ryder.lee@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Sj Huang <sj.huang@mediatek.com>,
Jianjun Wang <jianjun.wang@mediatek.com>,
<youlin.pei@mediatek.com>, <chuanjia.liu@mediatek.com>,
<qizhong.cheng@mediatek.com>, <sin_jieyang@mediatek.com>,
<drinkcat@chromium.org>, <Rex-BC.Chen@mediatek.com>,
<anson.chuang@mediatek.com>
Subject: [v8,6/7] PCI: mediatek-gen3: Add system PM support
Date: Wed, 24 Feb 2021 14:11:31 +0800 [thread overview]
Message-ID: <20210224061132.26526-7-jianjun.wang@mediatek.com> (raw)
In-Reply-To: <20210224061132.26526-1-jianjun.wang@mediatek.com>
Add suspend_noirq and resume_noirq callback functions to implement
PM system suspend hooks for MediaTek Gen3 PCIe controller.
When system suspend, trigger the PCIe link to L2 state and pull down
the PERST# pin, gating the clocks of MAC layer and power off the
physical layer for the sake of power saving.
When system resum, the PCIe link should be re-established and the
related control register values should be restored.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 84 +++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index fde9de591888..fd13540d37fe 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -45,6 +45,9 @@
#define PCIE_PE_RSTB BIT(3)
#define PCIE_LTSSM_STATUS_REG 0x150
+#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE 0x14
#define PCIE_LINK_STATUS_REG 0x154
#define PCIE_PORT_LINKUP BIT(8)
@@ -73,6 +76,9 @@
#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
+#define PCIE_ICMD_PM_REG 0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
#define PCIE_TRANS_TABLE_BASE_REG 0x800
#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
@@ -892,6 +898,83 @@ static int mtk_pcie_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
+{
+ u32 val;
+
+ val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
+ val |= PCIE_TURN_OFF_LINK;
+ writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
+
+ /* Check the link is L2 */
+ return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
+ (PCIE_LTSSM_STATE(val) ==
+ PCIE_LTSSM_STATE_L2_IDLE), 20,
+ 50 * USEC_PER_MSEC);
+}
+
+static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
+{
+ struct mtk_pcie_port *port = dev_get_drvdata(dev);
+ int err;
+ u32 val;
+
+ /* Trigger link to L2 state */
+ err = mtk_pcie_turn_off_link(port);
+ if (err) {
+ dev_err(port->dev, "can not enter L2 state\n");
+ return err;
+ }
+
+ /* Pull down the PERST# pin */
+ val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
+ val |= PCIE_PE_RSTB;
+ writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+ dev_dbg(port->dev, "enter L2 state success");
+
+ clk_bulk_disable_unprepare(port->num_clks, port->clks);
+
+ reset_control_assert(port->mac_reset);
+
+ phy_power_off(port->phy);
+ reset_control_assert(port->phy_reset);
+
+ return 0;
+}
+
+static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
+{
+ struct mtk_pcie_port *port = dev_get_drvdata(dev);
+ int err;
+
+ reset_control_deassert(port->phy_reset);
+ phy_power_on(port->phy);
+
+ reset_control_deassert(port->mac_reset);
+
+ err = clk_bulk_prepare_enable(port->num_clks, port->clks);
+ if (err) {
+ dev_dbg(dev, "failed to enable PCIe clocks\n");
+ return err;
+ }
+
+ err = mtk_pcie_startup_port(port);
+ if (err) {
+ dev_err(port->dev, "resume failed\n");
+ return err;
+ }
+
+ dev_dbg(port->dev, "resume done\n");
+
+ return 0;
+}
+
+static const struct dev_pm_ops mtk_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
+ mtk_pcie_resume_noirq)
+};
+
static const struct of_device_id mtk_pcie_of_match[] = {
{ .compatible = "mediatek,mt8192-pcie" },
{},
@@ -903,6 +986,7 @@ static struct platform_driver mtk_pcie_driver = {
.driver = {
.name = "mtk-pcie",
.of_match_table = mtk_pcie_of_match,
+ .pm = &mtk_pcie_pm_ops,
},
};
--
2.25.1
next prev parent reply other threads:[~2021-02-24 6:13 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-24 6:11 [v8,0/7] PCI: mediatek: Add new generation controller support Jianjun Wang
2021-02-24 6:11 ` [v8,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema Jianjun Wang
2021-03-06 20:09 ` Rob Herring
2021-02-24 6:11 ` [v8,2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-02-24 6:11 ` [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-02-24 13:36 ` Krzysztof Wilczyński
2021-02-25 3:07 ` Jianjun Wang
2021-03-11 12:38 ` Pali Rohár
2021-03-13 7:43 ` Jianjun Wang
2021-03-18 0:02 ` Pali Rohár
2021-03-18 5:48 ` Jianjun Wang
2021-03-19 18:53 ` Pali Rohár
2021-03-23 1:31 ` Jianjun Wang
2021-03-23 14:51 ` Pali Rohár
2021-03-29 22:58 ` Pali Rohár
2021-02-24 6:11 ` [v8,4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-02-24 14:24 ` Krzysztof Wilczyński
2021-02-25 3:10 ` Jianjun Wang
2021-03-09 11:10 ` Marc Zyngier
2021-03-10 3:05 ` Jianjun Wang
2021-02-24 6:11 ` [v8,5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-02-24 14:31 ` Krzysztof Wilczyński
2021-02-25 3:09 ` Jianjun Wang
2021-03-09 11:23 ` Marc Zyngier
2021-03-10 6:48 ` Jianjun Wang
[not found] ` <87a6rbxs4w.wl-maz@kernel.org>
2021-03-11 9:47 ` Jianjun Wang
2021-03-11 0:05 ` Pali Rohár
2021-03-11 8:19 ` Marc Zyngier
2021-03-11 9:50 ` Jianjun Wang
2021-02-24 6:11 ` Jianjun Wang [this message]
2021-02-24 14:10 ` [v8,6/7] PCI: mediatek-gen3: Add system PM support Krzysztof Wilczyński
2021-02-25 3:34 ` Jianjun Wang
2021-02-25 22:00 ` Krzysztof Wilczyński
2021-02-26 10:06 ` Jianjun Wang
2021-02-24 6:11 ` [v8,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang
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