From: Jianjun Wang <jianjun.wang@mediatek.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>, Marc Zyngier <maz@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Ryder Lee <ryder.lee@mediatek.com>
Cc: "Philipp Zabel" <p.zabel@pengutronix.de>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
youlin.pei@mediatek.com, chuanjia.liu@mediatek.com,
qizhong.cheng@mediatek.com, sin_jieyang@mediatek.com,
drinkcat@chromium.org, Rex-BC.Chen@mediatek.com,
anson.chuang@mediatek.com, "Krzysztof Wilczyski" <kw@linux.com>,
"Pali Rohár" <pali@kernel.org>
Subject: [v9,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema
Date: Wed, 24 Mar 2021 11:05:04 +0800 [thread overview]
Message-ID: <20210324030510.29177-2-jianjun.wang@mediatek.com> (raw)
In-Reply-To: <20210324030510.29177-1-jianjun.wang@mediatek.com>
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 181 ++++++++++++++++++
1 file changed, 181 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index 000000000000..e7b1f9892da4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+ - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |+
+ PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
+ and compatible with Gen2, Gen1 speed.
+
+ This PCIe controller supports up to 256 MSI vectors, the MSI hardware
+ block diagram is as follows:
+
+ +-----+
+ | GIC |
+ +-----+
+ ^
+ |
+ port->irq
+ |
+ +-+-+-+-+-+-+-+-+
+ |0|1|2|3|4|5|6|7| (PCIe intc)
+ +-+-+-+-+-+-+-+-+
+ ^ ^ ^
+ | | ... |
+ +-------+ +------+ +-----------+
+ | | |
+ +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
+ |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
+ +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
+ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
+ | | | | | | | | | | | | (MSI vectors)
+ | | | | | | | | | | | |
+
+ (MSI SET0) (MSI SET1) ... (MSI SET7)
+
+ With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
+ each set has its own address for MSI message, and supports 32 MSI vectors
+ to generate interrupt.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: mediatek,mt8192-pcie
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: pcie-mac
+
+ interrupts:
+ maxItems: 1
+
+ ranges:
+ minItems: 1
+ maxItems: 8
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: phy
+ - const: mac
+
+ clocks:
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: pl_250m
+ - const: tl_26m
+ - const: tl_96m
+ - const: tl_32k
+ - const: peri_26m
+ - const: top_133m
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller:
+ description: Interrupt controller node for handling legacy PCI interrupts.
+ type: object
+ properties:
+ '#address-cells':
+ const: 0
+ '#interrupt-cells':
+ const: 1
+ interrupt-controller: true
+
+ required:
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupt-controller
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - ranges
+ - clocks
+ - '#interrupt-cells'
+ - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@11230000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x00 0x11230000 0x00 0x4000>;
+ reg-names = "pcie-mac";
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0x00 0x12000000 0x00
+ 0x12000000 0x00 0x1000000>;
+ clocks = <&infracfg 44>,
+ <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m",
+ "tl_32k", "peri_26m", "top_133m";
+ assigned-clocks = <&topckgen 50>;
+ assigned-clock-parents = <&topckgen 91>;
+
+ phys = <&pciephy>;
+ phy-names = "pcie-phy";
+
+ resets = <&infracfg_rst 2>,
+ <&infracfg_rst 3>;
+ reset-names = "phy", "mac";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
--
2.25.1
next prev parent reply other threads:[~2021-03-24 3:06 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-24 3:05 [v9,0/7] PCI: mediatek: Add new generation controller support Jianjun Wang
2021-03-24 3:05 ` Jianjun Wang [this message]
2021-03-24 3:05 ` [v9,2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-03-24 9:09 ` Pali Rohár
2021-04-13 9:53 ` Lorenzo Pieralisi
2021-04-16 19:24 ` Bjorn Helgaas
2021-03-24 3:05 ` [v9,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-04-08 5:45 ` Jianjun Wang
2021-03-24 3:05 ` [v9,4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-03-24 16:17 ` Marc Zyngier
2021-03-24 3:05 ` [v9,5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-03-24 16:18 ` Marc Zyngier
2021-03-27 19:28 ` Pali Rohár
2021-03-27 19:44 ` Marc Zyngier
2021-03-27 20:29 ` Pali Rohár
2021-03-27 21:45 ` Marc Zyngier
2021-03-24 3:05 ` [v9,6/7] PCI: mediatek-gen3: Add system PM support Jianjun Wang
2021-03-24 3:05 ` [v9,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang
2021-04-16 19:21 ` [v9,0/7] PCI: mediatek: Add new generation controller support Bjorn Helgaas
2021-04-19 10:44 ` Lorenzo Pieralisi
2021-04-20 2:05 ` Jianjun Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210324030510.29177-2-jianjun.wang@mediatek.com \
--to=jianjun.wang@mediatek.com \
--cc=Rex-BC.Chen@mediatek.com \
--cc=anson.chuang@mediatek.com \
--cc=bhelgaas@google.com \
--cc=chuanjia.liu@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=matthias.bgg@gmail.com \
--cc=maz@kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=pali@kernel.org \
--cc=qizhong.cheng@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=ryder.lee@mediatek.com \
--cc=sin_jieyang@mediatek.com \
--cc=youlin.pei@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).