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From: "Pali Rohár" <>
To: Bjorn Helgaas <>,
	Lorenzo Pieralisi <>
Cc: "Marek Behún" <>,
	"Thomas Petazzoni" <>,
	"Stefan Roese" <>, "Phil Sutter" <>,
	"Mario Six" <>,
	"Stefan Chulski" <>,
Subject: Re: pci mvebu issue (memory controller)
Date: Sun, 3 Oct 2021 14:09:44 +0200	[thread overview]
Message-ID: <20211003120944.3lmwxylnhlp2kfj7@pali> (raw)
In-Reply-To: <>

Hello! See explanation below.

On Tuesday 09 February 2021 14:17:59 Marek Behún wrote:
> Hello Thomas,
> (sending this e-mail again because previously I sent it to Thomas' old
> e-mail address at free-electrons)
> we have enountered an issue with pci-mvebu driver and would like your
> opinion, since you are the author of commit
> After upgrading to new version of U-Boot on a Armada XP / 38x device,
> some WiFi cards stopped working in kernel. Ath10k driver, for example,
> could not load firmware into the card.
> We discovered that the issue is caused by U-Boot:
> - when U-Boot's pci_mvebu driver was converted to driver model API,
>   U-Boot started to configure PCIe registers not only for the newtork
>   adapter, but also for the Marvell Memory Controller (that you are
>   mentioning in your commit).
> - Since pci-mvebu driver in Linux is ignoring the Marvell Memory
>   Controller device, and U-Boot configures its registers (BARs and what
>   not), after kernel boots, the registers of this device are
>   incompatible with kernel, or something, and this causes problems for
>   the real PCIe device.
> - Stefan Roese has temporarily solved this issue with U-Boot commit
>   which basically just masks the Memory Controller's existence.
> - in Linux commit f4ac99011e54 ("pci: mvebu: no longer fake the slot
>   location of downstream devices") you mention that:
>    * On slot 0, a "Marvell Memory controller", identical on all PCIe
>      interfaces, and which isn't useful when the Marvell SoC is the PCIe
>      root complex (i.e, the normal case when we run Linux on the Marvell
>      SoC).
> What we are wondering is:
> - what does the Marvell Memory controller really do? Can it be used to
>   configure something? It clearly does something, because if it is
>   configured in U-Boot somehow but not in kernel, problems can occur.
> - is the best solution really just to ignore this device?
> - should U-Boot also start doing what commit f4ac99011e54 does? I.e.
>   to make sure that the real device is in slot 0, and Marvell Memory
>   Controller in slot 1.
> - why is Linux ignoring this device? It isn't even listed in lspci
>   output.
> Thanks,
> Marek


- Mysterious Marvell Memory Controller is PCIe Root Port (it can be
  verified by e.g. doing config space dump from U-Boot and then parse
  it via lspci)
- Config space of this PCIe device is mapped directly to the address
  space of PCIe controller (to offset zero)
- It has config space with Header Type 0 and Class Code 0x5080
- BARs configure PCIe controller itself, BAR0 must point to beginning of
  the SoC registers, other BARs to DDR memory address space
- Both U-Boot and Kernel pci mvebu drivers set Secondary Bus num to zero
- Patch which was fixing this issue disappeared from kernel

I think this explains all mentioned issues in previous email. Controller
driver configures registers for SoC and DDR and then PCI core/pnp
reconfigured them via config space to different values = no PCIe device
is working as PCIe controller it not able to access SoC registers and
DDR memory correctly anymore.

Bjorn, it is normal that PCIe Root Port device has Type 0 config space
and Class Code 0x5080 (Memory controller)? Because I thought that PCIe
Root Port device must have Class Code 0x6004 (PCI Bridge) with Type 1
config space.

And what should happen according to PCIe standards when both primary and
secondary bus numbers are configured to zeros? Or to other same numbers?

On primary bus is that Memory Controller == Root Port and on secondary
bus is endpoint card. Marvell has additional register for specifying
device number at which Root Port appears. And it looks like that if
primary and secondary bus numbers are same, then on this bus at Root
Port device address appears Root Port and on all other device addresses
appears endpoint card (which looks crazy if endpoint card is at all
possible BDF addresses where B=primary=secondary and D!=root_port).
But I have no idea what happens for other buses.

Seems that due to these issues pci-mvebu.c kernel driver filters access
to this PCIe Root Port device and uses pci-bridge-emul.c for providing
emulated PCIe Root Port device. It sets Root Port device address to 1
and allow access only to device address 0 (at which is endpoint card).

This issues appears in all Marvell SoCs. Here are just few lspci output
sent by different people in past. And All have one common thing: device
with "Root Port" and "Memory controller: Marvell" marking:

And that is not all. It looks like that this issue with Root Port /
Memory Controller was known also for kernel developers. In past, about
10 years ago, into kernel was merged following commit which explained it
and fixed class code from Memory Controller to PCI Bridge:

Apparently this patch completely disappeared as I'm not able find any
code with this comment or fixup in mainline kernel anymore.
Bjorn, Lorenzo, do you have any idea what happened?

  parent reply	other threads:[~2021-10-03 12:09 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-09 13:17 pci mvebu issue (memory controller) Marek Behún
2021-02-10  8:54 ` Thomas Petazzoni
2021-02-10 13:59   ` [EXT] " Stefan Chulski
2021-02-19 17:44     ` Pali Rohár
2021-03-04 18:29       ` Bjorn Helgaas
2021-11-01 18:07         ` Jason Gunthorpe
2021-10-03 12:09 ` Pali Rohár [this message]
  -- strict thread matches above, loose matches on Subject: below --
2021-02-08 15:08 Marek Behún

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