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From: Jason Gunthorpe <>
To: Bjorn Helgaas <>
Cc: "Pali Rohár" <>,
	"Stefan Chulski" <>,
	"Bjorn Helgaas" <>,
	"Thomas Petazzoni" <>,
	"Marek Behún" <>, "Stefan Roese" <>,
	"Phil Sutter" <>, "Mario Six" <>,
	"Lorenzo Pieralisi" <>,
	"" <>
Subject: Re: [EXT] Re: pci mvebu issue (memory controller)
Date: Mon, 1 Nov 2021 15:07:32 -0300	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <20210304182908.GA858065@bjorn-Precision-5520>

On Thu, Mar 04, 2021 at 12:29:08PM -0600, Bjorn Helgaas wrote:

> That's not much to go on.  Someone with more knowledge of the actual
> problem would have to weigh in on whether hiding a device is the best
> approach.

Since Pali asked..

The issue with this HW is the IP designers took an end port PCIe core
and glued it up to act as a root port without changing anything. This
is why it doesn't present a bridge config space. It is a *completely*
non compliant design.

The pci-mvebu host bridge driver is designged to fix this. It provides
a compliant PCI register view for a root port device using SW to
inspect config space operations and remaps the config space accesses
to their non-compliant positions within the SOC.

Hoping that the PCI core can directly drive this PCI device as a root
port without the above driver is just an endless sea of hacks.


  reply	other threads:[~2021-11-01 18:11 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-09 13:17 pci mvebu issue (memory controller) Marek Behún
2021-02-10  8:54 ` Thomas Petazzoni
2021-02-10 13:59   ` [EXT] " Stefan Chulski
2021-02-19 17:44     ` Pali Rohár
2021-03-04 18:29       ` Bjorn Helgaas
2021-11-01 18:07         ` Jason Gunthorpe [this message]
2021-10-03 12:09 ` Pali Rohár
     [not found] <20210602110703.ymdt6nxsjl7e6glk@pali>
2021-06-02 19:14 ` [EXT] " Bjorn Helgaas
2021-06-02 20:39   ` Pali Rohár
2021-06-02 21:01     ` Bjorn Helgaas
2021-06-02 21:13       ` Pali Rohár
2021-06-02 21:59         ` Marek Behún

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