From: "Pali Rohár" <pali@kernel.org>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Russell King <linux@armlinux.org.uk>,
Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Gregory Clement <gregory.clement@bootlin.com>,
Jason Gunthorpe <jgg@nvidia.com>,
linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup
Date: Tue, 2 Nov 2021 16:13:34 +0100 [thread overview]
Message-ID: <20211102151334.2pispbz6zfewworr@pali> (raw)
In-Reply-To: <20211102150201.GA11675@alpha.franken.de>
On Tuesday 02 November 2021 16:02:01 Thomas Bogendoerfer wrote:
> On Tue, Nov 02, 2021 at 11:00:34AM +0100, Pali Rohár wrote:
> > > > But I do not have this hardware to verify it.
> > >
> > > I still have a few Cobalt systems here.
> >
> > Perfect! It would help if you could provide 'lspci -nn -vv' output from
> > that system. In case you have very old version of lspci on that system
> > you could try to run it with '-xxxx' (or '-xxx') which prints hexdump
> > and I can parse it with local lspci.
>
> not sure, if you still needed:
>
> root@raq2:~# lspci -nn -vv
> 00:00.0 Host bridge [0600]: Marvell Technology Group Ltd. Device [11ab:4146] (rev 11)
> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
> Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx-
> Latency: 64, Cache Line Size: 32 bytes
> Interrupt: pin A routed to IRQ 0
> Region 1: Memory at 08000000 (32-bit, non-prefetchable) [size=128M]
> Region 2: Memory at 1c000000 (32-bit, non-prefetchable) [size=32M]
> Region 3: Memory at 1f000000 (32-bit, non-prefetchable) [size=16M]
> Region 4: Memory at 14000000 (32-bit, non-prefetchable) [size=4K]
> Region 5: I/O ports at 4000000 [disabled] [size=4K]
>
>
> root@raq2:~# lspci -xxxx
> 00:00.0 Host bridge: Marvell Technology Group Ltd. Device 4146 (rev 11)
> 00: ab 11 46 41 06 00 80 a2 11 00 80 05 08 40 00 00
^^ ^^ ^^
Here is class code
So it confirms that PCI Class code is 0580 which is Memory Controller.
And not Host Bridge as it should be.
If I put this hexdump into dump.txt and run 'lspci -F dump.txt -nn' then I see:
00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. Device [11ab:4146] (rev 11)
In your output above is "Host bridge" which means that quirk was applied:
00:00.0 Host bridge [0600]: Marvell Technology Group Ltd. Device [11ab:4146] (rev 11)
(I guess in 'lspci -nn -vv -b' should be Memory controller as lspci with
'-b' should not see that quirk change)
> 10: 00 00 00 00 00 00 00 08 00 00 00 1c 00 00 00 1f
> 20: 00 00 00 14 01 00 00 14 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
> 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2021-11-02 15:13 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 15:04 [PATCH] PCI: Marvell: Update PCIe fixup Pali Rohár
2021-11-01 16:27 ` Jason Gunthorpe
2021-11-01 17:56 ` Pali Rohár
2021-11-01 18:03 ` Jason Gunthorpe
2021-11-02 8:42 ` Thomas Bogendoerfer
2021-11-02 9:02 ` Pali Rohár
2021-11-02 9:47 ` Thomas Bogendoerfer
2021-11-02 10:00 ` Pali Rohár
2021-11-02 12:35 ` Maciej W. Rozycki
2021-11-02 12:58 ` Pali Rohár
2021-11-02 14:01 ` Maciej W. Rozycki
2021-11-02 14:49 ` Pali Rohár
2021-11-02 15:48 ` Pali Rohár
2021-11-02 17:03 ` Stefan Roese
2021-11-03 14:59 ` Maciej W. Rozycki
2021-11-03 14:49 ` Maciej W. Rozycki
2021-11-03 15:03 ` Pali Rohár
2021-11-02 15:02 ` Thomas Bogendoerfer
2021-11-02 15:13 ` Pali Rohár [this message]
2021-11-09 23:42 ` Pali Rohár
2021-11-10 8:55 ` Thomas Bogendoerfer
2021-11-02 17:12 ` [PATCH v2 1/2] ARM: " Pali Rohár
2021-11-09 22:53 ` Pali Rohár
2022-05-14 18:21 ` Pali Rohár
2022-07-07 18:31 ` Pali Rohár
2022-07-07 19:22 ` Russell King (Oracle)
2022-02-19 14:30 ` Pali Rohár
2022-07-18 10:34 ` Gregory CLEMENT
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