* [PATCH 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support
@ 2022-02-03 2:36 Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2022-02-03 2:36 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This series includes the patches to add basic support for the PCI endpoint
controller implemented in NX1 SoC.
Existing functions for Pro5 treat as "legacy" because the some registers
and initialization of NX1 is different from Pro5.
Kunihiko Hayashi (3):
dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
PCI: uniphier-ep: Add support for non-legacy SoC
PCI: uniphier-ep: Add compatible string and SoC-dependent data for NX1
SoC
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 ++--
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 139 ++++++++++++++++++---
2 files changed, 136 insertions(+), 25 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
2022-02-03 2:36 [PATCH 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
@ 2022-02-03 2:36 ` Kunihiko Hayashi
2022-02-03 13:50 ` Rob Herring
2022-02-03 2:36 ` [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 3/3] PCI: uniphier-ep: Add compatible string and SoC-dependent data for NX1 SoC Kunihiko Hayashi
2 siblings, 1 reply; 8+ messages in thread
From: Kunihiko Hayashi @ 2022-02-03 2:36 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Update PCI endpoint binding document for UniPhier NX1 SoC. Add a compatible
string, clock and reset lines for the SoC to the document.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index 179ab0858482..639bbeb8fa9d 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -20,7 +20,9 @@ allOf:
properties:
compatible:
- const: socionext,uniphier-pro5-pcie-ep
+ enum:
+ - socionext,uniphier-pro5-pcie-ep
+ - socionext,uniphier-nx1-pcie-ep
reg:
minItems: 4
@@ -41,20 +43,26 @@ properties:
- const: atu
clocks:
+ minItems: 1
maxItems: 2
clock-names:
- items:
- - const: gio
- - const: link
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for NX1
resets:
+ minItems: 1
maxItems: 2
reset-names:
- items:
- - const: gio
- - const: link
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for NX1
num-ib-windows:
const: 16
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC
2022-02-03 2:36 [PATCH 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
@ 2022-02-03 2:36 ` Kunihiko Hayashi
2022-02-04 16:06 ` Bjorn Helgaas
2022-02-03 2:36 ` [PATCH 3/3] PCI: uniphier-ep: Add compatible string and SoC-dependent data for NX1 SoC Kunihiko Hayashi
2 siblings, 1 reply; 8+ messages in thread
From: Kunihiko Hayashi @ 2022-02-03 2:36 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Define SoC data that includes pci_epc_features and boolean 'is_legacy'
to distinguish between legacy SoC (ex. Pro5) and non-legacy SoC.
Rename uniphier_pcie_init_ep() to uniphier_pcie_init_ep_legacy() for
initializing PCIe controller implemented in legacy SoC, add new
uniphier_pcie_init_ep() and uniphier_pcie_wait_ep() for non-legacy SoC
in the same method as pcie-uniphier driver.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 124 ++++++++++++++++++++++----
1 file changed, 106 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index 69810c6b0d58..073bdf7fcee3 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -10,6 +10,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
+#include <linux/iopoll.h>
#include <linux/of_device.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
@@ -31,6 +32,17 @@
#define PCL_RSTCTRL2 0x0024
#define PCL_RSTCTRL_PHY_RESET BIT(0)
+#define PCL_PINCTRL0 0x002c
+#define PCL_PERST_PLDN_REGEN BIT(12)
+#define PCL_PERST_NOE_REGEN BIT(11)
+#define PCL_PERST_OUT_REGEN BIT(8)
+#define PCL_PERST_PLDN_REGVAL BIT(4)
+#define PCL_PERST_NOE_REGVAL BIT(3)
+#define PCL_PERST_OUT_REGVAL BIT(0)
+
+#define PCL_PIPEMON 0x0044
+#define PCL_PCLK_ALIVE BIT(15)
+
#define PCL_MODE 0x8000
#define PCL_MODE_REGEN BIT(8)
#define PCL_MODE_REGVAL BIT(0)
@@ -51,6 +63,9 @@
#define PCL_APP_INTX 0x8074
#define PCL_APP_INTX_SYS_INT BIT(0)
+#define PCL_APP_PM0 0x8078
+#define PCL_SYS_AUX_PWR_DET BIT(8)
+
/* assertion time of INTx in usec */
#define PCL_INTX_WIDTH_USEC 30
@@ -60,7 +75,12 @@ struct uniphier_pcie_ep_priv {
struct clk *clk, *clk_gio;
struct reset_control *rst, *rst_gio;
struct phy *phy;
- const struct pci_epc_features *features;
+ const struct uniphier_pcie_ep_soc_data *data;
+};
+
+struct uniphier_pcie_ep_soc_data {
+ bool is_legacy;
+ const struct pci_epc_features features;
};
#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
@@ -91,7 +111,7 @@ static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
writel(val, priv->base + PCL_RSTCTRL2);
}
-static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
+static void uniphier_pcie_init_ep_legacy(struct uniphier_pcie_ep_priv *priv)
{
u32 val;
@@ -116,6 +136,63 @@ static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
msleep(100);
}
+static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
+{
+ u32 val;
+
+ if (priv->data->is_legacy) {
+ uniphier_pcie_init_ep_legacy(priv);
+ return;
+ }
+
+ /* set EP mode */
+ val = readl(priv->base + PCL_MODE);
+ val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
+ writel(val, priv->base + PCL_MODE);
+
+ /* use auxiliary power detection */
+ val = readl(priv->base + PCL_APP_PM0);
+ val |= PCL_SYS_AUX_PWR_DET;
+ writel(val, priv->base + PCL_APP_PM0);
+
+ /* assert PERST# */
+ val = readl(priv->base + PCL_PINCTRL0);
+ val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
+ | PCL_PERST_PLDN_REGVAL);
+ val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
+ | PCL_PERST_PLDN_REGEN;
+ writel(val, priv->base + PCL_PINCTRL0);
+
+ uniphier_pcie_ltssm_enable(priv, false);
+
+ usleep_range(100000, 200000);
+
+ /* deassert PERST# */
+ val = readl(priv->base + PCL_PINCTRL0);
+ val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
+ writel(val, priv->base + PCL_PINCTRL0);
+}
+
+static int uniphier_pcie_wait_ep(struct uniphier_pcie_ep_priv *priv)
+{
+ u32 status;
+ int ret;
+
+ if (priv->data->is_legacy)
+ return 0;
+
+ /* wait PIPE clock */
+ ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
+ status & PCL_PCLK_ALIVE, 100000, 1000000);
+ if (ret) {
+ dev_err(priv->pci.dev,
+ "Failed to initialize controller in EP mode\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int uniphier_pcie_start_link(struct dw_pcie *pci)
{
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
@@ -209,7 +286,7 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
- return priv->features;
+ return &priv->data->features;
}
static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
@@ -248,8 +325,14 @@ static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
uniphier_pcie_phy_reset(priv, false);
+ ret = uniphier_pcie_wait_ep(priv);
+ if (ret)
+ goto out_phy_exit;
+
return 0;
+out_phy_exit:
+ phy_exit(priv->phy);
out_rst_gio_assert:
reset_control_assert(priv->rst_gio);
out_rst_assert:
@@ -277,8 +360,8 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
- priv->features = of_device_get_match_data(dev);
- if (WARN_ON(!priv->features))
+ priv->data = of_device_get_match_data(dev);
+ if (WARN_ON(!priv->data))
return -EINVAL;
priv->pci.dev = dev;
@@ -288,13 +371,15 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- priv->clk_gio = devm_clk_get(dev, "gio");
- if (IS_ERR(priv->clk_gio))
- return PTR_ERR(priv->clk_gio);
+ if (priv->data->is_legacy) {
+ priv->clk_gio = devm_clk_get(dev, "gio");
+ if (IS_ERR(priv->clk_gio))
+ return PTR_ERR(priv->clk_gio);
- priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
- if (IS_ERR(priv->rst_gio))
- return PTR_ERR(priv->rst_gio);
+ priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
+ if (IS_ERR(priv->rst_gio))
+ return PTR_ERR(priv->rst_gio);
+ }
priv->clk = devm_clk_get(dev, "link");
if (IS_ERR(priv->clk))
@@ -321,13 +406,16 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
return dw_pcie_ep_init(&priv->pci.ep);
}
-static const struct pci_epc_features uniphier_pro5_data = {
- .linkup_notifier = false,
- .msi_capable = true,
- .msix_capable = false,
- .align = 1 << 16,
- .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
- .reserved_bar = BIT(BAR_4),
+static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
+ .is_legacy = true,
+ .features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .align = 1 << 16,
+ .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
+ .reserved_bar = BIT(BAR_4),
+ },
};
static const struct of_device_id uniphier_pcie_ep_match[] = {
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] PCI: uniphier-ep: Add compatible string and SoC-dependent data for NX1 SoC
2022-02-03 2:36 [PATCH 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC Kunihiko Hayashi
@ 2022-02-03 2:36 ` Kunihiko Hayashi
2 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2022-02-03 2:36 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add basic support for UniPhier NX1 SoC as non-legacy SoC. This includes
a compatible string and SoC-dependent data.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index 073bdf7fcee3..6e522724f7ed 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -418,11 +418,26 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
},
};
+static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
+ .is_legacy = false,
+ .features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .align = 1 << 12,
+ .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
+ },
+};
+
static const struct of_device_id uniphier_pcie_ep_match[] = {
{
.compatible = "socionext,uniphier-pro5-pcie-ep",
.data = &uniphier_pro5_data,
},
+ {
+ .compatible = "socionext,uniphier-nx1-pcie-ep",
+ .data = &uniphier_nx1_data,
+ },
{ /* sentinel */ },
};
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
2022-02-03 2:36 ` [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
@ 2022-02-03 13:50 ` Rob Herring
2022-02-04 4:22 ` Kunihiko Hayashi
0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2022-02-03 13:50 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: linux-pci, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczyński, Masami Hiramatsu, linux-arm-kernel,
Rob Herring, linux-kernel, devicetree
On Thu, 03 Feb 2022 11:36:24 +0900, Kunihiko Hayashi wrote:
> Update PCI endpoint binding document for UniPhier NX1 SoC. Add a compatible
> string, clock and reset lines for the SoC to the document.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> .../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml:24:9: [warning] too many spaces after hyphen (hyphens)
./Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml:25:9: [warning] too many spaces after hyphen (hyphens)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1587871
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
2022-02-03 13:50 ` Rob Herring
@ 2022-02-04 4:22 ` Kunihiko Hayashi
0 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2022-02-04 4:22 UTC (permalink / raw)
To: Rob Herring
Cc: linux-pci, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczyński, Masami Hiramatsu, linux-arm-kernel,
linux-kernel, devicetree
On 2022/02/03 22:50, Rob Herring wrote:
> On Thu, 03 Feb 2022 11:36:24 +0900, Kunihiko Hayashi wrote:
>> Update PCI endpoint binding document for UniPhier NX1 SoC. Add a
> compatible
>> string, clock and reset lines for the SoC to the document.
>>
>> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>> ---
>> .../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22
> +++++++++++++++-------
>> 1 file changed, 15 insertions(+), 7 deletions(-)
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml:24
> :9: [warning] too many spaces after hyphen (hyphens)
> ./Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml:25
> :9: [warning] too many spaces after hyphen (hyphens)
>
> dtschema/dtc warnings/errors:
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/1587871
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
I ran dt_binding_check, however, after installing 'yamllint' I've found
this warning. I'll resend it.
Thank you,
---
Best Regards
Kunihiko Hayashi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC
2022-02-03 2:36 ` [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC Kunihiko Hayashi
@ 2022-02-04 16:06 ` Bjorn Helgaas
2022-02-08 11:11 ` Kunihiko Hayashi
0 siblings, 1 reply; 8+ messages in thread
From: Bjorn Helgaas @ 2022-02-04 16:06 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu, linux-pci,
devicetree, linux-arm-kernel, linux-kernel
On Thu, Feb 03, 2022 at 11:36:25AM +0900, Kunihiko Hayashi wrote:
> Define SoC data that includes pci_epc_features and boolean 'is_legacy'
> to distinguish between legacy SoC (ex. Pro5) and non-legacy SoC.
I'm not a big fan of "legacy" as a description because it conveys very
little information. You're adding support for a "non-legacy" SoC, so
now there are "legacy" ones and "non-legacy" ones. Next year there
will be another new SoC, and then there will be *two* kinds of
"legacy" ones that must be distinguished plus the next "non-legacy"
one.
You mentioned "Pro5" as an example of "legacy," which is a good start.
Are there any others? If Pro5 is the only one, you could just use
"pro5" where you now use "legacy."
Bjorn
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC
2022-02-04 16:06 ` Bjorn Helgaas
@ 2022-02-08 11:11 ` Kunihiko Hayashi
0 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2022-02-08 11:11 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu, linux-pci,
devicetree, linux-arm-kernel, linux-kernel
Hi Bjorn,
Thank you for your comment.
On 2022/02/05 1:06, Bjorn Helgaas wrote:
> On Thu, Feb 03, 2022 at 11:36:25AM +0900, Kunihiko Hayashi wrote:
>> Define SoC data that includes pci_epc_features and boolean 'is_legacy'
>> to distinguish between legacy SoC (ex. Pro5) and non-legacy SoC.
>
> I'm not a big fan of "legacy" as a description because it conveys very
> little information. You're adding support for a "non-legacy" SoC, so
> now there are "legacy" ones and "non-legacy" ones. Next year there
> will be another new SoC, and then there will be *two* kinds of
> "legacy" ones that must be distinguished plus the next "non-legacy"
> one.
Make sense. There will be multiple different "legacy", so it isn't
desirable to distinguish SoCs by legacy and non-legacy.
> You mentioned "Pro5" as an example of "legacy," which is a good start.
> Are there any others? If Pro5 is the only one, you could just use
> "pro5" where you now use "legacy."
I see. In consideration of the future, I'll define callback functions
and prepare functions for each SoC.
And the "gio" clocks/resets are distinguished by the flag "has_gio".
Thank you,
---
Best Regards
Kunihiko Hayashi
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-02-08 11:32 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-03 2:36 [PATCH 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
2022-02-03 13:50 ` Rob Herring
2022-02-04 4:22 ` Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 2/3] PCI: uniphier-ep: Add support for non-legacy SoC Kunihiko Hayashi
2022-02-04 16:06 ` Bjorn Helgaas
2022-02-08 11:11 ` Kunihiko Hayashi
2022-02-03 2:36 ` [PATCH 3/3] PCI: uniphier-ep: Add compatible string and SoC-dependent data for NX1 SoC Kunihiko Hayashi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).