* [PATCH v2] PCI: qcom: Add support for handling MSIs from 8 endpoints
@ 2022-02-10 14:47 Manivannan Sadhasivam
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From: Manivannan Sadhasivam @ 2022-02-10 14:47 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas
Cc: svarbanov, bjorn.andersson, robh, linux-pci, linux-arm-msm,
linux-kernel, Manivannan Sadhasivam
The DWC controller used in the Qcom Platforms are capable of addressing the
MSIs generated from 8 different endpoints each with 32 vectors (256 in
total). Currently the driver is using the default value of addressing the
MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
num_vectors field of pcie_port structure.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v2:
* Rebased on top of v5.17-rc1
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index c19cd506ed3f..03e766f6937e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1556,6 +1556,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
pci->dev = dev;
pci->ops = &dw_pcie_ops;
pp = &pci->pp;
+ pp->num_vectors = MAX_MSI_IRQS;
pcie->pci = pci;
--
2.25.1
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