[PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints

linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed

* [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
@ 2021-12-14 10:13 Manivannan Sadhasivam
  2022-02-23 10:01 ` Lorenzo Pieralisi
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-12-14 10:13 UTC (permalink / raw)
  To: lorenzo.pieralisi, bhelgaas
  Cc: svarbanov, bjorn.andersson, robh, linux-pci, linux-arm-msm,
	linux-kernel, Manivannan Sadhasivam

The DWC controller used in the Qcom Platforms are capable of addressing the
MSIs generated from 8 different endpoints each with 32 vectors (256 in
total). Currently the driver is using the default value of addressing the
MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
num_vectors field of pcie_port structure.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1c3d1116bb60..8a4c08d815a5 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 	pci->dev = dev;
 	pci->ops = &dw_pcie_ops;
 	pp = &pci->pp;
+	pp->num_vectors = MAX_MSI_IRQS;
 
 	pcie->pci = pci;
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2021-12-14 10:13 [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Manivannan Sadhasivam
@ 2022-02-23 10:01 ` Lorenzo Pieralisi
  2022-03-14  5:22   ` Manivannan Sadhasivam
  2022-03-28 14:20   ` Manivannan Sadhasivam
  2022-02-23 10:03 ` Dmitry Baryshkov
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 9+ messages in thread
From: Lorenzo Pieralisi @ 2022-02-23 10:01 UTC (permalink / raw)
  To: Manivannan Sadhasivam, bjorn.andersson
  Cc: bhelgaas, svarbanov, robh, linux-pci, linux-arm-msm, linux-kernel

On Tue, Dec 14, 2021 at 03:43:19PM +0530, Manivannan Sadhasivam wrote:
> The DWC controller used in the Qcom Platforms are capable of addressing the
> MSIs generated from 8 different endpoints each with 32 vectors (256 in
> total). Currently the driver is using the default value of addressing the
> MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> num_vectors field of pcie_port structure.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>  1 file changed, 1 insertion(+)

Need an ACK from qcom maintainers.

Thanks,
Lorenzo

> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 1c3d1116bb60..8a4c08d815a5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>  	pci->dev = dev;
>  	pci->ops = &dw_pcie_ops;
>  	pp = &pci->pp;
> +	pp->num_vectors = MAX_MSI_IRQS;
>  
>  	pcie->pci = pci;
>  
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2022-02-23 10:01 ` Lorenzo Pieralisi
@ 2022-03-14  5:22   ` Manivannan Sadhasivam
  2022-03-28 14:20   ` Manivannan Sadhasivam
  1 sibling, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2022-03-14  5:22 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: bjorn.andersson, bhelgaas, svarbanov, robh, linux-pci,
	linux-arm-msm, linux-kernel

On Wed, Feb 23, 2022 at 10:01:45AM +0000, Lorenzo Pieralisi wrote:
> On Tue, Dec 14, 2021 at 03:43:19PM +0530, Manivannan Sadhasivam wrote:
> > The DWC controller used in the Qcom Platforms are capable of addressing the
> > MSIs generated from 8 different endpoints each with 32 vectors (256 in
> > total). Currently the driver is using the default value of addressing the
> > MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> > num_vectors field of pcie_port structure.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> >  1 file changed, 1 insertion(+)
> 
> Need an ACK from qcom maintainers.
> 

I think this one can be merged now.

Thanks,
Mani

> Thanks,
> Lorenzo
> 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 1c3d1116bb60..8a4c08d815a5 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> >  	pci->dev = dev;
> >  	pci->ops = &dw_pcie_ops;
> >  	pp = &pci->pp;
> > +	pp->num_vectors = MAX_MSI_IRQS;
> >  
> >  	pcie->pci = pci;
> >  
> > -- 
> > 2.25.1
> > 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2022-02-23 10:01 ` Lorenzo Pieralisi
  2022-03-14  5:22   ` Manivannan Sadhasivam
@ 2022-03-28 14:20   ` Manivannan Sadhasivam
  2022-03-28 14:39     ` Lorenzo Pieralisi
  2022-04-08  9:52     ` Lorenzo Pieralisi
  1 sibling, 2 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2022-03-28 14:20 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: bjorn.andersson, bhelgaas, svarbanov, robh, linux-pci,
	linux-arm-msm, linux-kernel

On Wed, Feb 23, 2022 at 10:01:45AM +0000, Lorenzo Pieralisi wrote:
> On Tue, Dec 14, 2021 at 03:43:19PM +0530, Manivannan Sadhasivam wrote:
> > The DWC controller used in the Qcom Platforms are capable of addressing the
> > MSIs generated from 8 different endpoints each with 32 vectors (256 in
> > total). Currently the driver is using the default value of addressing the
> > MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> > num_vectors field of pcie_port structure.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> >  1 file changed, 1 insertion(+)
> 
> Need an ACK from qcom maintainers.
> 

Looks like this patch was not applied eventhough the Acks were received.
Please let me know if I need to resubmit it for next cycle.

Thanks,
Mani

> Thanks,
> Lorenzo
> 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 1c3d1116bb60..8a4c08d815a5 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> >  	pci->dev = dev;
> >  	pci->ops = &dw_pcie_ops;
> >  	pp = &pci->pp;
> > +	pp->num_vectors = MAX_MSI_IRQS;
> >  
> >  	pcie->pci = pci;
> >  
> > -- 
> > 2.25.1
> > 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2022-03-28 14:20   ` Manivannan Sadhasivam
@ 2022-03-28 14:39     ` Lorenzo Pieralisi
  2022-04-08  9:52     ` Lorenzo Pieralisi
  1 sibling, 0 replies; 9+ messages in thread
From: Lorenzo Pieralisi @ 2022-03-28 14:39 UTC (permalink / raw)
  To: Manivannan Sadhasivam
  Cc: bjorn.andersson, bhelgaas, svarbanov, robh, linux-pci,
	linux-arm-msm, linux-kernel

On Mon, Mar 28, 2022 at 07:50:12PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Feb 23, 2022 at 10:01:45AM +0000, Lorenzo Pieralisi wrote:
> > On Tue, Dec 14, 2021 at 03:43:19PM +0530, Manivannan Sadhasivam wrote:
> > > The DWC controller used in the Qcom Platforms are capable of addressing the
> > > MSIs generated from 8 different endpoints each with 32 vectors (256 in
> > > total). Currently the driver is using the default value of addressing the
> > > MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> > > num_vectors field of pcie_port structure.
> > > 
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > >  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > 
> > Need an ACK from qcom maintainers.
> > 
> 
> Looks like this patch was not applied eventhough the Acks were received.
> Please let me know if I need to resubmit it for next cycle.

Sorry. I will merge it for the next cycle, nothing to do if it rebases
cleanly, otherwise I will ping you.

Thanks,
Lorenzo

> 
> Thanks,
> Mani
> 
> > Thanks,
> > Lorenzo
> > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 1c3d1116bb60..8a4c08d815a5 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> > >  	pci->dev = dev;
> > >  	pci->ops = &dw_pcie_ops;
> > >  	pp = &pci->pp;
> > > +	pp->num_vectors = MAX_MSI_IRQS;
> > >  
> > >  	pcie->pci = pci;
> > >  
> > > -- 
> > > 2.25.1
> > > 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2022-03-28 14:20   ` Manivannan Sadhasivam
  2022-03-28 14:39     ` Lorenzo Pieralisi
@ 2022-04-08  9:52     ` Lorenzo Pieralisi
  1 sibling, 0 replies; 9+ messages in thread
From: Lorenzo Pieralisi @ 2022-04-08  9:52 UTC (permalink / raw)
  To: Manivannan Sadhasivam
  Cc: bjorn.andersson, bhelgaas, svarbanov, robh, linux-pci,
	linux-arm-msm, linux-kernel

On Mon, Mar 28, 2022 at 07:50:12PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Feb 23, 2022 at 10:01:45AM +0000, Lorenzo Pieralisi wrote:
> > On Tue, Dec 14, 2021 at 03:43:19PM +0530, Manivannan Sadhasivam wrote:
> > > The DWC controller used in the Qcom Platforms are capable of addressing the
> > > MSIs generated from 8 different endpoints each with 32 vectors (256 in
> > > total). Currently the driver is using the default value of addressing the
> > > MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> > > num_vectors field of pcie_port structure.
> > > 
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > >  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > 
> > Need an ACK from qcom maintainers.
> > 
> 
> Looks like this patch was not applied eventhough the Acks were received.
> Please let me know if I need to resubmit it for next cycle.

There is no Acked-by tag on the latest version you posted:

https://lore.kernel.org/linux-pci/20220210144745.135721-1-manivannan.sadhasivam@linaro.org

it looks like the tags were given after v2 was posted, hence the
confusion.

I will apply the tags myself this time but what matters for me
is always the latest version posted, I archive the previous ones.

Lorenzo

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2021-12-14 10:13 [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Manivannan Sadhasivam
  2022-02-23 10:01 ` Lorenzo Pieralisi
@ 2022-02-23 10:03 ` Dmitry Baryshkov
  2022-02-23 10:30 ` Stanimir Varbanov
  2022-04-08 10:03 ` Lorenzo Pieralisi
  3 siblings, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2022-02-23 10:03 UTC (permalink / raw)
  To: Manivannan Sadhasivam, lorenzo.pieralisi, bhelgaas
  Cc: svarbanov, bjorn.andersson, robh, linux-pci, linux-arm-msm, linux-kernel

On 14/12/2021 13:13, Manivannan Sadhasivam wrote:
> The DWC controller used in the Qcom Platforms are capable of addressing the
> MSIs generated from 8 different endpoints each with 32 vectors (256 in
> total). Currently the driver is using the default value of addressing the
> MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> num_vectors field of pcie_port structure.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---
>   drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 1c3d1116bb60..8a4c08d815a5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>   	pci->dev = dev;
>   	pci->ops = &dw_pcie_ops;
>   	pp = &pci->pp;
> +	pp->num_vectors = MAX_MSI_IRQS;
>   
>   	pcie->pci = pci;
>   


-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2021-12-14 10:13 [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Manivannan Sadhasivam
  2022-02-23 10:01 ` Lorenzo Pieralisi
  2022-02-23 10:03 ` Dmitry Baryshkov
@ 2022-02-23 10:30 ` Stanimir Varbanov
  2022-04-08 10:03 ` Lorenzo Pieralisi
  3 siblings, 0 replies; 9+ messages in thread
From: Stanimir Varbanov @ 2022-02-23 10:30 UTC (permalink / raw)
  To: Manivannan Sadhasivam, lorenzo.pieralisi, bhelgaas
  Cc: bjorn.andersson, robh, linux-pci, linux-arm-msm, linux-kernel



On 12/14/21 12:13, Manivannan Sadhasivam wrote:
> The DWC controller used in the Qcom Platforms are capable of addressing the
> MSIs generated from 8 different endpoints each with 32 vectors (256 in
> total). Currently the driver is using the default value of addressing the
> MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> num_vectors field of pcie_port structure.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 1c3d1116bb60..8a4c08d815a5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>  	pci->dev = dev;
>  	pci->ops = &dw_pcie_ops;
>  	pp = &pci->pp;
> +	pp->num_vectors = MAX_MSI_IRQS;
>  
>  	pcie->pci = pci;
>  

-- 
regards,
Stan

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
  2021-12-14 10:13 [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Manivannan Sadhasivam
                   ` (2 preceding siblings ...)
  2022-02-23 10:30 ` Stanimir Varbanov
@ 2022-04-08 10:03 ` Lorenzo Pieralisi
  3 siblings, 0 replies; 9+ messages in thread
From: Lorenzo Pieralisi @ 2022-04-08 10:03 UTC (permalink / raw)
  To: Manivannan Sadhasivam, bhelgaas
  Cc: Lorenzo Pieralisi, linux-kernel, linux-arm-msm, bjorn.andersson,
	robh, linux-pci, svarbanov

On Tue, 14 Dec 2021 15:43:19 +0530, Manivannan Sadhasivam wrote:
> The DWC controller used in the Qcom Platforms are capable of addressing the
> MSIs generated from 8 different endpoints each with 32 vectors (256 in
> total). Currently the driver is using the default value of addressing the
> MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> num_vectors field of pcie_port structure.
> 
> 
> [...]

Applied to pci/qcom, thanks!

[1/1] PCI: qcom: Add support for handling MSIs from 8 endpoints
      https://git.kernel.org/lpieralisi/pci/c/20f1bfb8dd

Thanks,
Lorenzo

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-04-08 10:04 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-14 10:13 [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Manivannan Sadhasivam
2022-02-23 10:01 ` Lorenzo Pieralisi
2022-03-14  5:22   ` Manivannan Sadhasivam
2022-03-28 14:20   ` Manivannan Sadhasivam
2022-03-28 14:39     ` Lorenzo Pieralisi
2022-04-08  9:52     ` Lorenzo Pieralisi
2022-02-23 10:03 ` Dmitry Baryshkov
2022-02-23 10:30 ` Stanimir Varbanov
2022-04-08 10:03 ` Lorenzo Pieralisi

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).