* [PATCH v3 0/4] PCI: mvebu: Slot support @ 2022-03-25 9:38 Pali Rohár 2022-03-25 9:38 ` [PATCH v3 1/4] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Pali Rohár ` (3 more replies) 0 siblings, 4 replies; 11+ messages in thread From: Pali Rohár @ 2022-03-25 9:38 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King Cc: linux-pci, linux-arm-kernel, linux-kernel This patch series add slot support to pci-mvebu.c driver. It is based on branch pci/mvebu of git repository: https://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git Changes in v3: * Set 600 W when DT slot-power-limit-milliwatt > 600 W Changes in v2: * Dropped patch with PCI_EXP_SLTCAP_*_SHIFT macros as it is not needed anymore * Dropped patch "ARM: dts: turris-omnia: Set PCIe slot-power-limit-milliwatt properties" which was applied * Added support for PCIe 6.0 slot power limit encodings * Round down slot power limit value * Fix handling of slot power limit with scale x1.0 (0x00 value) * Use FIELD_PREP instead of _SHIFT macros * Changed commit message to Bjorn's suggestion * Changed comments in the code to match PCIe spec * Preserve user settings of PCI_EXP_SLTCTL_ASPL_DISABLE bit Pali Rohár (4): PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property PCI: mvebu: Add support for sending Set_Slot_Power_Limit message Documentation/devicetree/bindings/pci/pci.txt | 6 ++ drivers/pci/controller/pci-mvebu.c | 96 ++++++++++++++++++- drivers/pci/of.c | 64 +++++++++++++ drivers/pci/pci.h | 15 +++ include/uapi/linux/pci_regs.h | 1 + 5 files changed, 177 insertions(+), 5 deletions(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/4] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro 2022-03-25 9:38 [PATCH v3 0/4] PCI: mvebu: Slot support Pali Rohár @ 2022-03-25 9:38 ` Pali Rohár 2022-03-25 9:38 ` [PATCH v3 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property Pali Rohár ` (2 subsequent siblings) 3 siblings, 0 replies; 11+ messages in thread From: Pali Rohár @ 2022-03-25 9:38 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King Cc: linux-pci, linux-arm-kernel, linux-kernel Add macro defining Auto Slot Power Limit Disable bit in Slot Control Register. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com> --- include/uapi/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index bee1a9ed6e66..108f8523fa04 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -616,6 +616,7 @@ #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ +#define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */ #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */ #define PCI_EXP_SLTSTA 0x1a /* Slot Status */ #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property 2022-03-25 9:38 [PATCH v3 0/4] PCI: mvebu: Slot support Pali Rohár 2022-03-25 9:38 ` [PATCH v3 1/4] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Pali Rohár @ 2022-03-25 9:38 ` Pali Rohár 2022-04-08 10:31 ` Lorenzo Pieralisi 2022-03-25 9:38 ` [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property Pali Rohár 2022-03-25 9:38 ` [PATCH v3 4/4] PCI: mvebu: Add support for sending Set_Slot_Power_Limit message Pali Rohár 3 siblings, 1 reply; 11+ messages in thread From: Pali Rohár @ 2022-03-25 9:38 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King Cc: linux-pci, linux-arm-kernel, linux-kernel This property specifies slot power limit in mW unit. It is a form-factor and board specific value and must be initialized by hardware. Some PCIe controllers delegate this work to software to allow hardware flexibility and therefore this property basically specifies what should host bridge program into PCIe Slot Capabilities registers. The property needs to be specified in mW unit instead of the special format defined by Slot Capabilities (which encodes scaling factor or different unit). Host drivers should convert the value from mW to needed format. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- This change was already accepted into dt-schema repo by Rob Herring: https://github.com/devicetree-org/dt-schema/pull/66 --- Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..b0cc133ed00d 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -32,6 +32,12 @@ driver implementation may support the following properties: root port to downstream device and host bridge drivers can do programming which depends on CLKREQ signal existence. For example, programming root port not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. +- slot-power-limit-milliwatt: + If present, this property specifies slot power limit in milliwatts. Host + drivers can parse this property and use it for programming Root Port or host + bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages + through the Root Port or host bridge when transitioning PCIe link from a + non-DL_Up Status to a DL_Up Status. PCI-PCI Bridge properties ------------------------- -- 2.20.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property 2022-03-25 9:38 ` [PATCH v3 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property Pali Rohár @ 2022-04-08 10:31 ` Lorenzo Pieralisi 0 siblings, 0 replies; 11+ messages in thread From: Lorenzo Pieralisi @ 2022-04-08 10:31 UTC (permalink / raw) To: Pali Rohár, Rob Herring Cc: Bjorn Helgaas, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, linux-pci, linux-arm-kernel, linux-kernel On Fri, Mar 25, 2022 at 10:38:25AM +0100, Pali Rohár wrote: > This property specifies slot power limit in mW unit. It is a form-factor > and board specific value and must be initialized by hardware. > > Some PCIe controllers delegate this work to software to allow hardware > flexibility and therefore this property basically specifies what should > host bridge program into PCIe Slot Capabilities registers. > > The property needs to be specified in mW unit instead of the special format > defined by Slot Capabilities (which encodes scaling factor or different > unit). Host drivers should convert the value from mW to needed format. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Signed-off-by: Marek Behún <kabel@kernel.org> > > --- > This change was already accepted into dt-schema repo by Rob Herring: > https://github.com/devicetree-org/dt-schema/pull/66 Is there a way I can check a DT binding was pulled into the schema without having to read the patch (eg just checking Rob's Acked/Reviewed tags ?) I think this patch should have been posted to devicetree@vger.kernel.org, by the way. Lorenzo > Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt > index 6a8f2874a24d..b0cc133ed00d 100644 > --- a/Documentation/devicetree/bindings/pci/pci.txt > +++ b/Documentation/devicetree/bindings/pci/pci.txt > @@ -32,6 +32,12 @@ driver implementation may support the following properties: > root port to downstream device and host bridge drivers can do programming > which depends on CLKREQ signal existence. For example, programming root port > not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. > +- slot-power-limit-milliwatt: > + If present, this property specifies slot power limit in milliwatts. Host > + drivers can parse this property and use it for programming Root Port or host > + bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages > + through the Root Port or host bridge when transitioning PCIe link from a > + non-DL_Up Status to a DL_Up Status. > > PCI-PCI Bridge properties > ------------------------- > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property 2022-03-25 9:38 [PATCH v3 0/4] PCI: mvebu: Slot support Pali Rohár 2022-03-25 9:38 ` [PATCH v3 1/4] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Pali Rohár 2022-03-25 9:38 ` [PATCH v3 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property Pali Rohár @ 2022-03-25 9:38 ` Pali Rohár 2022-04-08 15:27 ` Bjorn Helgaas 2022-03-25 9:38 ` [PATCH v3 4/4] PCI: mvebu: Add support for sending Set_Slot_Power_Limit message Pali Rohár 3 siblings, 1 reply; 11+ messages in thread From: Pali Rohár @ 2022-03-25 9:38 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King Cc: linux-pci, linux-arm-kernel, linux-kernel Add function of_pci_get_slot_power_limit(), which parses the 'slot-power-limit-milliwatt' DT property, returning the value in milliwatts and in format ready for the PCIe Slot Capabilities Register. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes in v3: * Set 600 W when DT slot-power-limit-milliwatt > 600 W Changes in v2: * Added support for PCIe 6.0 slot power limit encodings * Round down slot power limit value --- drivers/pci/of.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 15 +++++++++++ 2 files changed, 79 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index cb2e8351c2cc..5ebff26edd41 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -633,3 +633,67 @@ int of_pci_get_max_link_speed(struct device_node *node) return max_link_speed; } EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); + +/** + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" + * property. + * + * @node: device tree node with the slot power limit information + * @slot_power_limit_value: pointer where the value should be stored in PCIe + * Slot Capabilities Register format + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe + * Slot Capabilities Register format + * + * Returns the slot power limit in milliwatts and if @slot_power_limit_value + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and + * scale in format used by PCIe Slot Capabilities Register. + * + * If the property is not found or is invalid, returns 0. + */ +u32 of_pci_get_slot_power_limit(struct device_node *node, + u8 *slot_power_limit_value, + u8 *slot_power_limit_scale) +{ + u32 slot_power_limit_mw; + u8 value, scale; + + if (of_property_read_u32(node, "slot-power-limit-milliwatt", + &slot_power_limit_mw)) + slot_power_limit_mw = 0; + + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ + if (slot_power_limit_mw == 0) { + value = 0x00; + scale = 0; + } else if (slot_power_limit_mw <= 255) { + value = slot_power_limit_mw; + scale = 3; + } else if (slot_power_limit_mw <= 255*10) { + value = slot_power_limit_mw / 10; + scale = 2; + } else if (slot_power_limit_mw <= 255*100) { + value = slot_power_limit_mw / 100; + scale = 1; + } else if (slot_power_limit_mw <= 239*1000) { + value = slot_power_limit_mw / 1000; + scale = 0; + } else if (slot_power_limit_mw <= 250*1000) { + value = 0xF0; + scale = 0; + } else if (slot_power_limit_mw <= 600*1000) { + value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; + scale = 0; + } else { + value = 0xFE; + scale = 0; + } + + if (slot_power_limit_value) + *slot_power_limit_value = value; + + if (slot_power_limit_scale) + *slot_power_limit_scale = scale; + + return slot_power_limit_mw; +} +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 3d60cabde1a1..e10cdec6c56e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -627,6 +627,9 @@ struct device_node; int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); int of_pci_get_max_link_speed(struct device_node *node); +u32 of_pci_get_slot_power_limit(struct device_node *node, + u8 *slot_power_limit_value, + u8 *slot_power_limit_scale); void pci_set_of_node(struct pci_dev *dev); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); @@ -653,6 +656,18 @@ of_pci_get_max_link_speed(struct device_node *node) return -EINVAL; } +static inline u32 +of_pci_get_slot_power_limit(struct device_node *node, + u8 *slot_power_limit_value, + u8 *slot_power_limit_scale) +{ + if (slot_power_limit_value) + *slot_power_limit_value = 0; + if (slot_power_limit_scale) + *slot_power_limit_scale = 0; + return 0; +} + static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } -- 2.20.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property 2022-03-25 9:38 ` [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property Pali Rohár @ 2022-04-08 15:27 ` Bjorn Helgaas 2022-04-11 11:14 ` Pali Rohár 2022-10-27 19:05 ` Bjorn Helgaas 0 siblings, 2 replies; 11+ messages in thread From: Bjorn Helgaas @ 2022-04-08 15:27 UTC (permalink / raw) To: Pali Rohár Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, linux-pci, linux-arm-kernel, linux-kernel On Fri, Mar 25, 2022 at 10:38:26AM +0100, Pali Rohár wrote: > Add function of_pci_get_slot_power_limit(), which parses the > 'slot-power-limit-milliwatt' DT property, returning the value in > milliwatts and in format ready for the PCIe Slot Capabilities Register. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Signed-off-by: Marek Behún <kabel@kernel.org> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > Changes in v3: > * Set 600 W when DT slot-power-limit-milliwatt > 600 W > Changes in v2: > * Added support for PCIe 6.0 slot power limit encodings > * Round down slot power limit value > --- > drivers/pci/of.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++ > drivers/pci/pci.h | 15 +++++++++++ > 2 files changed, 79 insertions(+) > > diff --git a/drivers/pci/of.c b/drivers/pci/of.c > index cb2e8351c2cc..5ebff26edd41 100644 > --- a/drivers/pci/of.c > +++ b/drivers/pci/of.c > @@ -633,3 +633,67 @@ int of_pci_get_max_link_speed(struct device_node *node) > return max_link_speed; > } > EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); > + > +/** > + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" > + * property. > + * > + * @node: device tree node with the slot power limit information > + * @slot_power_limit_value: pointer where the value should be stored in PCIe > + * Slot Capabilities Register format > + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe > + * Slot Capabilities Register format > + * > + * Returns the slot power limit in milliwatts and if @slot_power_limit_value > + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and > + * scale in format used by PCIe Slot Capabilities Register. > + * > + * If the property is not found or is invalid, returns 0. > + */ > +u32 of_pci_get_slot_power_limit(struct device_node *node, > + u8 *slot_power_limit_value, > + u8 *slot_power_limit_scale) > +{ > + u32 slot_power_limit_mw; > + u8 value, scale; > + > + if (of_property_read_u32(node, "slot-power-limit-milliwatt", > + &slot_power_limit_mw)) > + slot_power_limit_mw = 0; > + > + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ > + if (slot_power_limit_mw == 0) { > + value = 0x00; > + scale = 0; > + } else if (slot_power_limit_mw <= 255) { > + value = slot_power_limit_mw; > + scale = 3; > + } else if (slot_power_limit_mw <= 255*10) { > + value = slot_power_limit_mw / 10; > + scale = 2; > + } else if (slot_power_limit_mw <= 255*100) { > + value = slot_power_limit_mw / 100; > + scale = 1; > + } else if (slot_power_limit_mw <= 239*1000) { > + value = slot_power_limit_mw / 1000; > + scale = 0; > + } else if (slot_power_limit_mw <= 250*1000) { > + value = 0xF0; > + scale = 0; I think the spec is poorly worded here. PCIe r6.0, sec 7.5.3.9, says: F0h > 239 W and <= 250 W Slot Power Limit I don't think it's meaningful for the spec to include a range here. The amount of power the slot can supply has a single maximum. I suspect the *intent* of F0h/00b is that a device in the slot may consume up to 250W. Your code above would mean that slot_power_limit_mw == 245,000 would cause the slot to advertise F0h/00b (250W), which seems wrong. I think we should do something like this instead: scale = 0; if (slot_power_limit_mw >= 600*1000) { value = 0xFE; slot_power_limit_mw = 600*1000; } else if (slot_power_limit_mw >= 575*1000) { value = 0xFD; slot_power_limit_mw = 575*1000; } ... I raised an issue with the PCI SIG about this. > + } else if (slot_power_limit_mw <= 600*1000) { > + value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; > + scale = 0; > + } else { > + value = 0xFE; > + scale = 0; > + } > + > + if (slot_power_limit_value) > + *slot_power_limit_value = value; > + > + if (slot_power_limit_scale) > + *slot_power_limit_scale = scale; > + > + return slot_power_limit_mw; If the DT tells us 800W is available, we'll store (FEh/00b), which means the slot can advertise to a downstream device that 600W is available. I think that's correct, since the current spec doesn't provide a way to encode any value larger than 600W. But the function still returns 800,000 mW, which means the next patch will print: %s: Slot power limit 800.0W even though it programs Slot Capabilities to advertise 600W. That's why I suggested setting slot_power_limit_mw = 600*1000 above. > +} > +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 3d60cabde1a1..e10cdec6c56e 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -627,6 +627,9 @@ struct device_node; > int of_pci_parse_bus_range(struct device_node *node, struct resource *res); > int of_get_pci_domain_nr(struct device_node *node); > int of_pci_get_max_link_speed(struct device_node *node); > +u32 of_pci_get_slot_power_limit(struct device_node *node, > + u8 *slot_power_limit_value, > + u8 *slot_power_limit_scale); > void pci_set_of_node(struct pci_dev *dev); > void pci_release_of_node(struct pci_dev *dev); > void pci_set_bus_of_node(struct pci_bus *bus); > @@ -653,6 +656,18 @@ of_pci_get_max_link_speed(struct device_node *node) > return -EINVAL; > } > > +static inline u32 > +of_pci_get_slot_power_limit(struct device_node *node, > + u8 *slot_power_limit_value, > + u8 *slot_power_limit_scale) > +{ > + if (slot_power_limit_value) > + *slot_power_limit_value = 0; > + if (slot_power_limit_scale) > + *slot_power_limit_scale = 0; > + return 0; > +} > + > static inline void pci_set_of_node(struct pci_dev *dev) { } > static inline void pci_release_of_node(struct pci_dev *dev) { } > static inline void pci_set_bus_of_node(struct pci_bus *bus) { } > -- > 2.20.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property 2022-04-08 15:27 ` Bjorn Helgaas @ 2022-04-11 11:14 ` Pali Rohár 2022-04-11 19:02 ` Pali Rohár 2022-04-11 19:54 ` Bjorn Helgaas 2022-10-27 19:05 ` Bjorn Helgaas 1 sibling, 2 replies; 11+ messages in thread From: Pali Rohár @ 2022-04-11 11:14 UTC (permalink / raw) To: Bjorn Helgaas Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, linux-pci, linux-arm-kernel, linux-kernel On Friday 08 April 2022 10:27:50 Bjorn Helgaas wrote: > On Fri, Mar 25, 2022 at 10:38:26AM +0100, Pali Rohár wrote: > > Add function of_pci_get_slot_power_limit(), which parses the > > 'slot-power-limit-milliwatt' DT property, returning the value in > > milliwatts and in format ready for the PCIe Slot Capabilities Register. > > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > Signed-off-by: Marek Behún <kabel@kernel.org> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > Changes in v3: > > * Set 600 W when DT slot-power-limit-milliwatt > 600 W > > Changes in v2: > > * Added support for PCIe 6.0 slot power limit encodings > > * Round down slot power limit value > > --- > > drivers/pci/of.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++ > > drivers/pci/pci.h | 15 +++++++++++ > > 2 files changed, 79 insertions(+) > > > > diff --git a/drivers/pci/of.c b/drivers/pci/of.c > > index cb2e8351c2cc..5ebff26edd41 100644 > > --- a/drivers/pci/of.c > > +++ b/drivers/pci/of.c > > @@ -633,3 +633,67 @@ int of_pci_get_max_link_speed(struct device_node *node) > > return max_link_speed; > > } > > EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); > > + > > +/** > > + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" > > + * property. > > + * > > + * @node: device tree node with the slot power limit information > > + * @slot_power_limit_value: pointer where the value should be stored in PCIe > > + * Slot Capabilities Register format > > + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe > > + * Slot Capabilities Register format > > + * > > + * Returns the slot power limit in milliwatts and if @slot_power_limit_value > > + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and > > + * scale in format used by PCIe Slot Capabilities Register. > > + * > > + * If the property is not found or is invalid, returns 0. > > + */ > > +u32 of_pci_get_slot_power_limit(struct device_node *node, > > + u8 *slot_power_limit_value, > > + u8 *slot_power_limit_scale) > > +{ > > + u32 slot_power_limit_mw; > > + u8 value, scale; > > + > > + if (of_property_read_u32(node, "slot-power-limit-milliwatt", > > + &slot_power_limit_mw)) > > + slot_power_limit_mw = 0; > > + > > + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ > > + if (slot_power_limit_mw == 0) { > > + value = 0x00; > > + scale = 0; > > + } else if (slot_power_limit_mw <= 255) { > > + value = slot_power_limit_mw; > > + scale = 3; > > + } else if (slot_power_limit_mw <= 255*10) { > > + value = slot_power_limit_mw / 10; > > + scale = 2; > > + } else if (slot_power_limit_mw <= 255*100) { > > + value = slot_power_limit_mw / 100; > > + scale = 1; > > + } else if (slot_power_limit_mw <= 239*1000) { > > + value = slot_power_limit_mw / 1000; > > + scale = 0; > > + } else if (slot_power_limit_mw <= 250*1000) { > > + value = 0xF0; > > + scale = 0; > > I think the spec is poorly worded here. PCIe r6.0, sec 7.5.3.9, says: > > F0h > 239 W and <= 250 W Slot Power Limit > > I don't think it's meaningful for the spec to include a range here. > The amount of power the slot can supply has a single maximum. I > suspect the *intent* of F0h/00b is that a device in the slot may > consume up to 250W. > > Your code above would mean that slot_power_limit_mw == 245,000 would > cause the slot to advertise F0h/00b (250W), which seems wrong. So for slot_power_limit_mw == 245 W we should set following values? slot_power_limit_mw = 239 W value = 0xF0 scale = 0 > I think we should do something like this instead: > > scale = 0; > if (slot_power_limit_mw >= 600*1000) { > value = 0xFE; > slot_power_limit_mw = 600*1000; > } else if (slot_power_limit_mw >= 575*1000) { > value = 0xFD; > slot_power_limit_mw = 575*1000; > } ... This is already implemented in branch: } else if (slot_power_limit_mw <= 600*1000) { value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; scale = 0; I will just add reducing of final slot_power_limit_mw value. > I raised an issue with the PCI SIG about this. > > > + } else if (slot_power_limit_mw <= 600*1000) { > > + value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; > > + scale = 0; > > + } else { > > + value = 0xFE; > > + scale = 0; > > + } > > + > > + if (slot_power_limit_value) > > + *slot_power_limit_value = value; > > + > > + if (slot_power_limit_scale) > > + *slot_power_limit_scale = scale; > > + > > + return slot_power_limit_mw; > > If the DT tells us 800W is available, we'll store (FEh/00b), which > means the slot can advertise to a downstream device that 600W is > available. I think that's correct, since the current spec doesn't > provide a way to encode any value larger than 600W. > > But the function still returns 800,000 mW, which means the next patch will > print: > > %s: Slot power limit 800.0W > > even though it programs Slot Capabilities to advertise 600W. > That's why I suggested setting slot_power_limit_mw = 600*1000 above. Ok, I will update slot_power_limit_mw value in next patch version. > > +} > > +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > > index 3d60cabde1a1..e10cdec6c56e 100644 > > --- a/drivers/pci/pci.h > > +++ b/drivers/pci/pci.h > > @@ -627,6 +627,9 @@ struct device_node; > > int of_pci_parse_bus_range(struct device_node *node, struct resource *res); > > int of_get_pci_domain_nr(struct device_node *node); > > int of_pci_get_max_link_speed(struct device_node *node); > > +u32 of_pci_get_slot_power_limit(struct device_node *node, > > + u8 *slot_power_limit_value, > > + u8 *slot_power_limit_scale); > > void pci_set_of_node(struct pci_dev *dev); > > void pci_release_of_node(struct pci_dev *dev); > > void pci_set_bus_of_node(struct pci_bus *bus); > > @@ -653,6 +656,18 @@ of_pci_get_max_link_speed(struct device_node *node) > > return -EINVAL; > > } > > > > +static inline u32 > > +of_pci_get_slot_power_limit(struct device_node *node, > > + u8 *slot_power_limit_value, > > + u8 *slot_power_limit_scale) > > +{ > > + if (slot_power_limit_value) > > + *slot_power_limit_value = 0; > > + if (slot_power_limit_scale) > > + *slot_power_limit_scale = 0; > > + return 0; > > +} > > + > > static inline void pci_set_of_node(struct pci_dev *dev) { } > > static inline void pci_release_of_node(struct pci_dev *dev) { } > > static inline void pci_set_bus_of_node(struct pci_bus *bus) { } > > -- > > 2.20.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property 2022-04-11 11:14 ` Pali Rohár @ 2022-04-11 19:02 ` Pali Rohár 2022-04-11 19:54 ` Bjorn Helgaas 1 sibling, 0 replies; 11+ messages in thread From: Pali Rohár @ 2022-04-11 19:02 UTC (permalink / raw) To: Bjorn Helgaas Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, linux-pci, linux-arm-kernel, linux-kernel On Monday 11 April 2022 13:14:07 Pali Rohár wrote: > On Friday 08 April 2022 10:27:50 Bjorn Helgaas wrote: > > On Fri, Mar 25, 2022 at 10:38:26AM +0100, Pali Rohár wrote: > > > Add function of_pci_get_slot_power_limit(), which parses the > > > 'slot-power-limit-milliwatt' DT property, returning the value in > > > milliwatts and in format ready for the PCIe Slot Capabilities Register. > > > > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > > Signed-off-by: Marek Behún <kabel@kernel.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > --- > > > Changes in v3: > > > * Set 600 W when DT slot-power-limit-milliwatt > 600 W > > > Changes in v2: > > > * Added support for PCIe 6.0 slot power limit encodings > > > * Round down slot power limit value > > > --- > > > drivers/pci/of.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++ > > > drivers/pci/pci.h | 15 +++++++++++ > > > 2 files changed, 79 insertions(+) > > > > > > diff --git a/drivers/pci/of.c b/drivers/pci/of.c > > > index cb2e8351c2cc..5ebff26edd41 100644 > > > --- a/drivers/pci/of.c > > > +++ b/drivers/pci/of.c > > > @@ -633,3 +633,67 @@ int of_pci_get_max_link_speed(struct device_node *node) > > > return max_link_speed; > > > } > > > EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); > > > + > > > +/** > > > + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" > > > + * property. > > > + * > > > + * @node: device tree node with the slot power limit information > > > + * @slot_power_limit_value: pointer where the value should be stored in PCIe > > > + * Slot Capabilities Register format > > > + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe > > > + * Slot Capabilities Register format > > > + * > > > + * Returns the slot power limit in milliwatts and if @slot_power_limit_value > > > + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and > > > + * scale in format used by PCIe Slot Capabilities Register. > > > + * > > > + * If the property is not found or is invalid, returns 0. > > > + */ > > > +u32 of_pci_get_slot_power_limit(struct device_node *node, > > > + u8 *slot_power_limit_value, > > > + u8 *slot_power_limit_scale) > > > +{ > > > + u32 slot_power_limit_mw; > > > + u8 value, scale; > > > + > > > + if (of_property_read_u32(node, "slot-power-limit-milliwatt", > > > + &slot_power_limit_mw)) > > > + slot_power_limit_mw = 0; > > > + > > > + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ > > > + if (slot_power_limit_mw == 0) { > > > + value = 0x00; > > > + scale = 0; > > > + } else if (slot_power_limit_mw <= 255) { > > > + value = slot_power_limit_mw; > > > + scale = 3; > > > + } else if (slot_power_limit_mw <= 255*10) { > > > + value = slot_power_limit_mw / 10; > > > + scale = 2; > > > + } else if (slot_power_limit_mw <= 255*100) { > > > + value = slot_power_limit_mw / 100; > > > + scale = 1; > > > + } else if (slot_power_limit_mw <= 239*1000) { > > > + value = slot_power_limit_mw / 1000; > > > + scale = 0; > > > + } else if (slot_power_limit_mw <= 250*1000) { > > > + value = 0xF0; > > > + scale = 0; > > > > I think the spec is poorly worded here. PCIe r6.0, sec 7.5.3.9, says: > > > > F0h > 239 W and <= 250 W Slot Power Limit > > > > I don't think it's meaningful for the spec to include a range here. > > The amount of power the slot can supply has a single maximum. I > > suspect the *intent* of F0h/00b is that a device in the slot may > > consume up to 250W. > > > > Your code above would mean that slot_power_limit_mw == 245,000 would > > cause the slot to advertise F0h/00b (250W), which seems wrong. > > So for slot_power_limit_mw == 245 W we should set following values? > > slot_power_limit_mw = 239 W > value = 0xF0 > scale = 0 I changed it in v4 > > I think we should do something like this instead: > > > > scale = 0; > > if (slot_power_limit_mw >= 600*1000) { > > value = 0xFE; > > slot_power_limit_mw = 600*1000; > > } else if (slot_power_limit_mw >= 575*1000) { > > value = 0xFD; > > slot_power_limit_mw = 575*1000; > > } ... > > This is already implemented in branch: > > } else if (slot_power_limit_mw <= 600*1000) { > value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; > scale = 0; > > I will just add reducing of final slot_power_limit_mw value. > > > I raised an issue with the PCI SIG about this. > > > > > + } else if (slot_power_limit_mw <= 600*1000) { > > > + value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; > > > + scale = 0; > > > + } else { > > > + value = 0xFE; > > > + scale = 0; > > > + } > > > + > > > + if (slot_power_limit_value) > > > + *slot_power_limit_value = value; > > > + > > > + if (slot_power_limit_scale) > > > + *slot_power_limit_scale = scale; > > > + > > > + return slot_power_limit_mw; > > > > If the DT tells us 800W is available, we'll store (FEh/00b), which > > means the slot can advertise to a downstream device that 600W is > > available. I think that's correct, since the current spec doesn't > > provide a way to encode any value larger than 600W. > > > > But the function still returns 800,000 mW, which means the next patch will > > print: > > > > %s: Slot power limit 800.0W > > > > even though it programs Slot Capabilities to advertise 600W. > > That's why I suggested setting slot_power_limit_mw = 600*1000 above. > > Ok, I will update slot_power_limit_mw value in next patch version. And also fixed this in v4. Please review v4 if is is OK now. > > > +} > > > +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); > > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > > > index 3d60cabde1a1..e10cdec6c56e 100644 > > > --- a/drivers/pci/pci.h > > > +++ b/drivers/pci/pci.h > > > @@ -627,6 +627,9 @@ struct device_node; > > > int of_pci_parse_bus_range(struct device_node *node, struct resource *res); > > > int of_get_pci_domain_nr(struct device_node *node); > > > int of_pci_get_max_link_speed(struct device_node *node); > > > +u32 of_pci_get_slot_power_limit(struct device_node *node, > > > + u8 *slot_power_limit_value, > > > + u8 *slot_power_limit_scale); > > > void pci_set_of_node(struct pci_dev *dev); > > > void pci_release_of_node(struct pci_dev *dev); > > > void pci_set_bus_of_node(struct pci_bus *bus); > > > @@ -653,6 +656,18 @@ of_pci_get_max_link_speed(struct device_node *node) > > > return -EINVAL; > > > } > > > > > > +static inline u32 > > > +of_pci_get_slot_power_limit(struct device_node *node, > > > + u8 *slot_power_limit_value, > > > + u8 *slot_power_limit_scale) > > > +{ > > > + if (slot_power_limit_value) > > > + *slot_power_limit_value = 0; > > > + if (slot_power_limit_scale) > > > + *slot_power_limit_scale = 0; > > > + return 0; > > > +} > > > + > > > static inline void pci_set_of_node(struct pci_dev *dev) { } > > > static inline void pci_release_of_node(struct pci_dev *dev) { } > > > static inline void pci_set_bus_of_node(struct pci_bus *bus) { } > > > -- > > > 2.20.1 > > > > > > > > > _______________________________________________ > > > linux-arm-kernel mailing list > > > linux-arm-kernel@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property 2022-04-11 11:14 ` Pali Rohár 2022-04-11 19:02 ` Pali Rohár @ 2022-04-11 19:54 ` Bjorn Helgaas 1 sibling, 0 replies; 11+ messages in thread From: Bjorn Helgaas @ 2022-04-11 19:54 UTC (permalink / raw) To: Pali Rohár Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, linux-pci, linux-arm-kernel, linux-kernel On Mon, Apr 11, 2022 at 01:14:07PM +0200, Pali Rohár wrote: > On Friday 08 April 2022 10:27:50 Bjorn Helgaas wrote: > > On Fri, Mar 25, 2022 at 10:38:26AM +0100, Pali Rohár wrote: > > > Add function of_pci_get_slot_power_limit(), which parses the > > > 'slot-power-limit-milliwatt' DT property, returning the value in > > > milliwatts and in format ready for the PCIe Slot Capabilities Register. > > > > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > > Signed-off-by: Marek Behún <kabel@kernel.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > --- > > > Changes in v3: > > > * Set 600 W when DT slot-power-limit-milliwatt > 600 W > > > Changes in v2: > > > * Added support for PCIe 6.0 slot power limit encodings > > > * Round down slot power limit value > > > --- > > > drivers/pci/of.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++ > > > drivers/pci/pci.h | 15 +++++++++++ > > > 2 files changed, 79 insertions(+) > > > > > > diff --git a/drivers/pci/of.c b/drivers/pci/of.c > > > index cb2e8351c2cc..5ebff26edd41 100644 > > > --- a/drivers/pci/of.c > > > +++ b/drivers/pci/of.c > > > @@ -633,3 +633,67 @@ int of_pci_get_max_link_speed(struct device_node *node) > > > return max_link_speed; > > > } > > > EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); > > > + > > > +/** > > > + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" > > > + * property. > > > + * > > > + * @node: device tree node with the slot power limit information > > > + * @slot_power_limit_value: pointer where the value should be stored in PCIe > > > + * Slot Capabilities Register format > > > + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe > > > + * Slot Capabilities Register format > > > + * > > > + * Returns the slot power limit in milliwatts and if @slot_power_limit_value > > > + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and > > > + * scale in format used by PCIe Slot Capabilities Register. > > > + * > > > + * If the property is not found or is invalid, returns 0. > > > + */ > > > +u32 of_pci_get_slot_power_limit(struct device_node *node, > > > + u8 *slot_power_limit_value, > > > + u8 *slot_power_limit_scale) > > > +{ > > > + u32 slot_power_limit_mw; > > > + u8 value, scale; > > > + > > > + if (of_property_read_u32(node, "slot-power-limit-milliwatt", > > > + &slot_power_limit_mw)) > > > + slot_power_limit_mw = 0; > > > + > > > + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ > > > + if (slot_power_limit_mw == 0) { > > > + value = 0x00; > > > + scale = 0; > > > + } else if (slot_power_limit_mw <= 255) { > > > + value = slot_power_limit_mw; > > > + scale = 3; > > > + } else if (slot_power_limit_mw <= 255*10) { > > > + value = slot_power_limit_mw / 10; > > > + scale = 2; > > > + } else if (slot_power_limit_mw <= 255*100) { > > > + value = slot_power_limit_mw / 100; > > > + scale = 1; > > > + } else if (slot_power_limit_mw <= 239*1000) { > > > + value = slot_power_limit_mw / 1000; > > > + scale = 0; > > > + } else if (slot_power_limit_mw <= 250*1000) { > > > + value = 0xF0; > > > + scale = 0; > > > > I think the spec is poorly worded here. PCIe r6.0, sec 7.5.3.9, says: > > > > F0h > 239 W and <= 250 W Slot Power Limit > > > > I don't think it's meaningful for the spec to include a range here. > > The amount of power the slot can supply has a single maximum. I > > suspect the *intent* of F0h/00b is that a device in the slot may > > consume up to 250W. > > > > Your code above would mean that slot_power_limit_mw == 245,000 would > > cause the slot to advertise F0h/00b (250W), which seems wrong. > > So for slot_power_limit_mw == 245 W we should set following values? > > slot_power_limit_mw = 239 W > value = 0xF0 > scale = 0 I think Slot Cap should never advertise more power than the slot can supply. So if the DT tells us the slot can supply 245 W, I don't think Slot Cap should advertise that it can supply 250 W. I think we should drop down to the next lower possible value, which is 239 W (value 0xEF, scale 0). I think this is what your v4 does. > > I think we should do something like this instead: > > > > scale = 0; > > if (slot_power_limit_mw >= 600*1000) { > > value = 0xFE; > > slot_power_limit_mw = 600*1000; > > } else if (slot_power_limit_mw >= 575*1000) { > > value = 0xFD; > > slot_power_limit_mw = 575*1000; > > } ... > > This is already implemented in branch: > > } else if (slot_power_limit_mw <= 600*1000) { > value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; > scale = 0; OK, I was thinking there was a hole here, but I guess not. I think do think it's easier to read and verify if it's structured as "the slot can supply at least X, so advertise X", as opposed to "the slot can supply X or less, so advertise Y". Bjorn ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property 2022-04-08 15:27 ` Bjorn Helgaas 2022-04-11 11:14 ` Pali Rohár @ 2022-10-27 19:05 ` Bjorn Helgaas 1 sibling, 0 replies; 11+ messages in thread From: Bjorn Helgaas @ 2022-10-27 19:05 UTC (permalink / raw) To: Pali Rohár Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, linux-pci, linux-arm-kernel, linux-kernel On Fri, Apr 08, 2022 at 10:27:50AM -0500, Bjorn Helgaas wrote: > On Fri, Mar 25, 2022 at 10:38:26AM +0100, Pali Rohár wrote: > > Add function of_pci_get_slot_power_limit(), which parses the > > 'slot-power-limit-milliwatt' DT property, returning the value in > > milliwatts and in format ready for the PCIe Slot Capabilities Register. > ... > I think the spec is poorly worded here. PCIe r6.0, sec 7.5.3.9, says: > > F0h > 239 W and <= 250 W Slot Power Limit > > I don't think it's meaningful for the spec to include a range here. > The amount of power the slot can supply has a single maximum. I > suspect the *intent* of F0h/00b is that a device in the slot may > consume up to 250W. > > Your code above would mean that slot_power_limit_mw == 245,000 would > cause the slot to advertise F0h/00b (250W), which seems wrong. > > I think we should do something like this instead: > > scale = 0; > if (slot_power_limit_mw >= 600*1000) { > value = 0xFE; > slot_power_limit_mw = 600*1000; > } else if (slot_power_limit_mw >= 575*1000) { > value = 0xFD; > slot_power_limit_mw = 575*1000; > } ... > > I raised an issue with the PCI SIG about this. Just to close the loop here, a PCI SIG moderator agrees that F0h should mean up to 250 W may be consumed. My question as posed: 7.5.3.9 defines alternate encodings for Slot Power Limit Values F0h-FEh when Slot Power Limit Scale is 00b. For example: F0h > 239 W and <= 250 W Slot Power Limit How should an Upstream Port interpret a Set_Slot_Power_Limit message with a payload of Scale 00b and Value F0h? Obviously the device may consume up to 239 W. Is it allowed to consume 240 W? 245 W? 250 W? If it is allowed to consume 250 W, I suggest that there is no reason to mention 239 W at all, and I suggest that the table be reworked so each encoding specifies a single limit, e.g., F0h 250 W Slot Power Limit F1h 275 W Slot Power Limit This question arises because a Linux Device Tree may specify the amount of power a slot can supply. If the Device Tree says a slot can supply 245 W, how should Slot Power Limit Value/Scale be programmed? F0h/00b because 245 is between 239 and 250? Or EFh/00b (239 W) because F0h/00b actually means the slot must be able to supply 250 W and this slot can't do that? PCI-SIG MODERATOR RESPONSE: A setting of F0h should be interpreted as allowing up to 250 W to be consumed. I agree that it makes sense to list the limits as: F0h 250 W Slot Power Limit F1h 275 W Slot Power Limit ... I will propose your suggested simplification to the Protocol Work Group. For PCI-SIG members, this discussion is at https://forum.pcisig.com/viewtopic.php?f=616&p=3914#p3914 Bjorn ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 4/4] PCI: mvebu: Add support for sending Set_Slot_Power_Limit message 2022-03-25 9:38 [PATCH v3 0/4] PCI: mvebu: Slot support Pali Rohár ` (2 preceding siblings ...) 2022-03-25 9:38 ` [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property Pali Rohár @ 2022-03-25 9:38 ` Pali Rohár 3 siblings, 0 replies; 11+ messages in thread From: Pali Rohár @ 2022-03-25 9:38 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Andrew Lunn, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King Cc: linux-pci, linux-arm-kernel, linux-kernel If DT supplies the 'slot-power-limit-milliwatt' property, program the value in the Slot Power Limit in the Slot Capabilities register and program the Root Port to send a Set_Slot_Power_Limit Message when the Link transitions to DL_Up. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes in v2: * Fix handling of slot power limit with scale x1.0 (0x00 value) * Use FIELD_PREP instead of _SHIFT macros * Changed commit message to Bjorn's suggestion * Changed comments in the code to match PCIe spec * Preserve user settings of PCI_EXP_SLTCTL_ASPL_DISABLE bit --- drivers/pci/controller/pci-mvebu.c | 96 ++++++++++++++++++++++++++++-- 1 file changed, 91 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index a75d2b9196f9..26ae7c29fece 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -8,6 +8,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/gpio.h> @@ -66,6 +67,12 @@ #define PCIE_STAT_BUS 0xff00 #define PCIE_STAT_DEV 0x1f0000 #define PCIE_STAT_LINK_DOWN BIT(0) +#define PCIE_SSPL_OFF 0x1a0c +#define PCIE_SSPL_VALUE_SHIFT 0 +#define PCIE_SSPL_VALUE_MASK GENMASK(7, 0) +#define PCIE_SSPL_SCALE_SHIFT 8 +#define PCIE_SSPL_SCALE_MASK GENMASK(9, 8) +#define PCIE_SSPL_ENABLE BIT(16) #define PCIE_RC_RTSTA 0x1a14 #define PCIE_DEBUG_CTRL 0x1a60 #define PCIE_DEBUG_SOFT_RESET BIT(20) @@ -111,6 +118,8 @@ struct mvebu_pcie_port { struct mvebu_pcie_window iowin; u32 saved_pcie_stat; struct resource regs; + u8 slot_power_limit_value; + u8 slot_power_limit_scale; struct irq_domain *intx_irq_domain; raw_spinlock_t irq_lock; int intx_irq; @@ -239,7 +248,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) { - u32 ctrl, lnkcap, cmd, dev_rev, unmask; + u32 ctrl, lnkcap, cmd, dev_rev, unmask, sspl; /* Setup PCIe controller to Root Complex mode. */ ctrl = mvebu_readl(port, PCIE_CTRL_OFF); @@ -292,6 +301,20 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) /* Point PCIe unit MBUS decode windows to DRAM space. */ mvebu_pcie_setup_wins(port); + /* + * Program Root Port to automatically send Set_Slot_Power_Limit + * PCIe Message when changing status from Dl_Down to Dl_Up and valid + * slot power limit was specified. + */ + sspl = mvebu_readl(port, PCIE_SSPL_OFF); + sspl &= ~(PCIE_SSPL_VALUE_MASK | PCIE_SSPL_SCALE_MASK | PCIE_SSPL_ENABLE); + if (port->slot_power_limit_value) { + sspl |= port->slot_power_limit_value << PCIE_SSPL_VALUE_SHIFT; + sspl |= port->slot_power_limit_scale << PCIE_SSPL_SCALE_SHIFT; + sspl |= PCIE_SSPL_ENABLE; + } + mvebu_writel(port, sspl, PCIE_SSPL_OFF); + /* Mask all interrupt sources. */ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); @@ -628,9 +651,23 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, (PCI_EXP_LNKSTA_DLLLA << 16) : 0); break; - case PCI_EXP_SLTCTL: - *value = PCI_EXP_SLTSTA_PDS << 16; + case PCI_EXP_SLTCTL: { + u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta); + u32 val = 0; + /* + * When slot power limit was not specified in DT then + * ASPL_DISABLE bit is stored only in emulated config space. + * Otherwise reflect status of PCIE_SSPL_ENABLE bit in HW. + */ + if (!port->slot_power_limit_value) + val |= slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE; + else if (!(mvebu_readl(port, PCIE_SSPL_OFF) & PCIE_SSPL_ENABLE)) + val |= PCI_EXP_SLTCTL_ASPL_DISABLE; + /* This callback is 32-bit and in high bits is slot status. */ + val |= slotsta << 16; + *value = val; break; + } case PCI_EXP_RTSTA: *value = mvebu_readl(port, PCIE_RC_RTSTA); @@ -774,6 +811,22 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); break; + case PCI_EXP_SLTCTL: + /* + * Allow to change PCIE_SSPL_ENABLE bit only when slot power + * limit was specified in DT and configured into HW. + */ + if ((mask & PCI_EXP_SLTCTL_ASPL_DISABLE) && + port->slot_power_limit_value) { + u32 sspl = mvebu_readl(port, PCIE_SSPL_OFF); + if (new & PCI_EXP_SLTCTL_ASPL_DISABLE) + sspl &= ~PCIE_SSPL_ENABLE; + else + sspl |= PCIE_SSPL_ENABLE; + mvebu_writel(port, sspl, PCIE_SSPL_OFF); + } + break; + case PCI_EXP_RTSTA: /* * PME Status bit in Root Status Register (PCIE_RC_RTSTA) @@ -868,8 +921,26 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) /* * Older mvebu hardware provides PCIe Capability structure only in * version 1. New hardware provides it in version 2. + * Enable slot support which is emulated. */ - bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver); + bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver | PCI_EXP_FLAGS_SLOT); + + /* + * Set Presence Detect State bit permanently as there is no support for + * unplugging PCIe card from the slot. Assume that PCIe card is always + * connected in slot. + * + * Set physical slot number to port+1 as mvebu ports are indexed from + * zero and zero value is reserved for ports within the same silicon + * as Root Port which is not mvebu case. + * + * Also set correct slot power limit. + */ + bridge->pcie_conf.slotcap = cpu_to_le32( + FIELD_PREP(PCI_EXP_SLTCAP_SPLV, port->slot_power_limit_value) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLS, port->slot_power_limit_scale) | + FIELD_PREP(PCI_EXP_SLTCAP_PSN, port->port+1)); + bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); bridge->subsystem_vendor_id = ssdev_id & 0xffff; bridge->subsystem_id = ssdev_id >> 16; @@ -1191,6 +1262,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, { struct device *dev = &pcie->pdev->dev; enum of_gpio_flags flags; + u32 slot_power_limit; int reset_gpio, ret; u32 num_lanes; @@ -1291,6 +1363,15 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, port->reset_gpio = gpio_to_desc(reset_gpio); } + slot_power_limit = of_pci_get_slot_power_limit(child, + &port->slot_power_limit_value, + &port->slot_power_limit_scale); + if (slot_power_limit) + dev_info(dev, "%s: Slot power limit %u.%uW\n", + port->name, + slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + port->clk = of_clk_get_by_name(child, NULL); if (IS_ERR(port->clk)) { dev_err(dev, "%s: cannot get clock\n", port->name); @@ -1587,7 +1668,7 @@ static int mvebu_pcie_remove(struct platform_device *pdev) { struct mvebu_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); - u32 cmd; + u32 cmd, sspl; int i; /* Remove PCI bus with all devices. */ @@ -1624,6 +1705,11 @@ static int mvebu_pcie_remove(struct platform_device *pdev) /* Free config space for emulated root bridge. */ pci_bridge_emul_cleanup(&port->bridge); + /* Disable sending Set_Slot_Power_Limit PCIe Message. */ + sspl = mvebu_readl(port, PCIE_SSPL_OFF); + sspl &= ~(PCIE_SSPL_VALUE_MASK | PCIE_SSPL_SCALE_MASK | PCIE_SSPL_ENABLE); + mvebu_writel(port, sspl, PCIE_SSPL_OFF); + /* Disable and clear BARs and windows. */ mvebu_pcie_disable_wins(port); -- 2.20.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-10-27 19:06 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-25 9:38 [PATCH v3 0/4] PCI: mvebu: Slot support Pali Rohár 2022-03-25 9:38 ` [PATCH v3 1/4] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Pali Rohár 2022-03-25 9:38 ` [PATCH v3 2/4] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property Pali Rohár 2022-04-08 10:31 ` Lorenzo Pieralisi 2022-03-25 9:38 ` [PATCH v3 3/4] PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property Pali Rohár 2022-04-08 15:27 ` Bjorn Helgaas 2022-04-11 11:14 ` Pali Rohár 2022-04-11 19:02 ` Pali Rohár 2022-04-11 19:54 ` Bjorn Helgaas 2022-10-27 19:05 ` Bjorn Helgaas 2022-03-25 9:38 ` [PATCH v3 4/4] PCI: mvebu: Add support for sending Set_Slot_Power_Limit message Pali Rohár
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