* [PATCH 0/6] RZN1 USB Host support
@ 2022-04-12 9:40 Herve Codina
2022-04-12 9:40 ` [PATCH 1/6] PCI: rcar-gen2: Add support for clocks Herve Codina
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
Hi,
This series add support for the USB Host controllers available on
RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located
behind a bridge.
Regards,
Herve
Herve Codina (6):
PCI: rcar-gen2: Add support for clocks
dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032
PCI: rcar-gen2: Add R9A06G032 support
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
.../devicetree/bindings/pci/pci-rcar-gen2.txt | 4 +-
arch/arm/boot/dts/r9a06g032.dtsi | 46 +++++++++++++++++++
drivers/pci/controller/pci-rcar-gen2.c | 30 +++++++++++-
3 files changed, 77 insertions(+), 3 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/6] PCI: rcar-gen2: Add support for clocks
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
@ 2022-04-12 9:40 ` Herve Codina
2022-04-12 15:50 ` Rob Herring
2022-04-12 9:40 ` [PATCH 2/6] dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
The PCI rcar-gen2 does not call any clk_prepare_enable().
This lead to an access failure when the driver tries to access
the IP (at least on a RZ/N1D platform).
Prepare and enable clocks using the bulk version of
clk_prepare_enable() in order to prepare and enable all clocks
attached to this device.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/pci/controller/pci-rcar-gen2.c | 28 ++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
index 35804ea394fd..528bc3780e01 100644
--- a/drivers/pci/controller/pci-rcar-gen2.c
+++ b/drivers/pci/controller/pci-rcar-gen2.c
@@ -8,6 +8,7 @@
* Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
*/
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -99,6 +100,8 @@ struct rcar_pci {
struct resource mem_res;
struct resource *cfg_res;
int irq;
+ struct clk_bulk_data *clocks;
+ int nclocks;
};
/* PCI configuration space operations */
@@ -282,6 +285,7 @@ static int rcar_pci_probe(struct platform_device *pdev)
struct rcar_pci *priv;
struct pci_host_bridge *bridge;
void __iomem *reg;
+ int ret;
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
if (!bridge)
@@ -305,13 +309,25 @@ static int rcar_pci_probe(struct platform_device *pdev)
priv->mem_res = *mem_res;
priv->cfg_res = cfg_res;
+ ret = devm_clk_bulk_get_all(dev, &priv->clocks);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clocks %d\n", ret);
+ return ret;
+ }
+ priv->nclocks = ret;
+
+ ret = clk_bulk_prepare_enable(priv->nclocks, priv->clocks);
+ if (ret)
+ return ret;
+
priv->irq = platform_get_irq(pdev, 0);
priv->reg = reg;
priv->dev = dev;
if (priv->irq < 0) {
dev_err(dev, "no valid irq found\n");
- return priv->irq;
+ ret = priv->irq;
+ goto disable_clocks;
}
bridge->ops = &rcar_pci_ops;
@@ -320,7 +336,15 @@ static int rcar_pci_probe(struct platform_device *pdev)
rcar_pci_setup(priv);
- return pci_host_probe(bridge);
+ ret = pci_host_probe(bridge);
+ if (ret < 0)
+ goto disable_clocks;
+
+ return 0;
+
+disable_clocks:
+ clk_bulk_disable_unprepare(priv->nclocks, priv->clocks);
+ return ret;
}
static const struct of_device_id rcar_pci_of_match[] = {
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/6] dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
2022-04-12 9:40 ` [PATCH 1/6] PCI: rcar-gen2: Add support for clocks Herve Codina
@ 2022-04-12 9:40 ` Herve Codina
2022-04-12 9:40 ` [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support Herve Codina
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
Add internal PCI bridge support for the r9a06g032 SoC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index aeba38f0a387..098ea12e6c95 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -15,7 +15,9 @@ Required properties:
"renesas,pci-r8a7793" for the R8A7793 SoC;
"renesas,pci-r8a7794" for the R8A7794 SoC;
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
- RZ/G1 compatible device.
+ RZ/G1 compatible device;
+ "renesas,pci-r9a06g032" for the R9A06G032 (RZ/N1D) SoC;
+ "renesas,pci-rzn1" for a generic RZ/N1 compatible device.
When compatible with the generic version, nodes must list the
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
2022-04-12 9:40 ` [PATCH 1/6] PCI: rcar-gen2: Add support for clocks Herve Codina
2022-04-12 9:40 ` [PATCH 2/6] dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
@ 2022-04-12 9:40 ` Herve Codina
2022-04-12 10:05 ` Miquel Raynal
2022-04-13 9:08 ` Sergey Shtylyov
2022-04-12 9:40 ` [PATCH 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
` (2 subsequent siblings)
5 siblings, 2 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
Add Renesas R9A06G032 SoC support to the Renesas R-Car gen2 PCI
bridge driver.
The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible
with the one available in the R-Car Gen2 family.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/pci/controller/pci-rcar-gen2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
index 528bc3780e01..586e4785a57f 100644
--- a/drivers/pci/controller/pci-rcar-gen2.c
+++ b/drivers/pci/controller/pci-rcar-gen2.c
@@ -352,6 +352,8 @@ static const struct of_device_id rcar_pci_of_match[] = {
{ .compatible = "renesas,pci-r8a7791", },
{ .compatible = "renesas,pci-r8a7794", },
{ .compatible = "renesas,pci-rcar-gen2", },
+ { .compatible = "renesas,pci-r9a06g032", },
+ { .compatible = "renesas,pci-rzn1", },
{ },
};
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
` (2 preceding siblings ...)
2022-04-12 9:40 ` [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support Herve Codina
@ 2022-04-12 9:40 ` Herve Codina
2022-04-12 9:40 ` [PATCH 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
2022-04-12 9:40 ` [PATCH 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
5 siblings, 0 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
Add the device node for the r9a06g032 internal PCI bridge device.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 636a6ab31c58..c6a99b2a8fb3 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -211,6 +211,34 @@ gic: interrupt-controller@44101000 {
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ pci_usb: pci@40030000 {
+ compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+ device_type = "pci";
+ clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+ <&sysctrl R9A06G032_HCLK_USBPM>,
+ <&sysctrl R9A06G032_CLK_PCI_USB>;
+ clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
+ reg = <0x40030000 0xc00>,
+ <0x40020000 0x1100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
+ /* Should map all possible DDR as inbound ranges, but
+ * the IP only supports a 256MB, 512MB, or 1GB window.
+ * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+ */
+ dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
timer {
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/6] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
` (3 preceding siblings ...)
2022-04-12 9:40 ` [PATCH 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
@ 2022-04-12 9:40 ` Herve Codina
2022-04-12 9:40 ` [PATCH 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
5 siblings, 0 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
Define the r9a06g032 generic part of the USB PHY device node.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index c6a99b2a8fb3..c9336dc4888a 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
clock-frequency = <0>;
};
+ usbphy: usbphy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
` (4 preceding siblings ...)
2022-04-12 9:40 ` [PATCH 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
@ 2022-04-12 9:40 ` Herve Codina
5 siblings, 0 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-12 9:40 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal,
Herve Codina
Describe the PCI USB devices that are behind the PCI bridge, adding
necessary links to the USB PHY device.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index c9336dc4888a..75e45fd6bedb 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -244,6 +244,18 @@ pci_usb: pci@40030000 {
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ };
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support
2022-04-12 9:40 ` [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support Herve Codina
@ 2022-04-12 10:05 ` Miquel Raynal
2022-04-13 9:08 ` Sergey Shtylyov
1 sibling, 0 replies; 12+ messages in thread
From: Miquel Raynal @ 2022-04-12 10:05 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, linux-renesas-soc, devicetree, linux-kernel,
Thomas Petazzoni, Clement Leger
Hi Herve,
herve.codina@bootlin.com wrote on Tue, 12 Apr 2022 11:40:26 +0200:
> Add Renesas R9A06G032 SoC support to the Renesas R-Car gen2 PCI
> bridge driver.
> The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible
> with the one available in the R-Car Gen2 family.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> drivers/pci/controller/pci-rcar-gen2.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
> index 528bc3780e01..586e4785a57f 100644
> --- a/drivers/pci/controller/pci-rcar-gen2.c
> +++ b/drivers/pci/controller/pci-rcar-gen2.c
> @@ -352,6 +352,8 @@ static const struct of_device_id rcar_pci_of_match[] = {
> { .compatible = "renesas,pci-r8a7791", },
> { .compatible = "renesas,pci-r8a7794", },
> { .compatible = "renesas,pci-rcar-gen2", },
> + { .compatible = "renesas,pci-r9a06g032", },
> + { .compatible = "renesas,pci-rzn1", },
I don't think you don't yet need to match against the two, matching
against pci-rzn1 is enough for now, until we discover that something is
specific in the r9a06g032 family and we need to handle something else
of course.
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] PCI: rcar-gen2: Add support for clocks
2022-04-12 9:40 ` [PATCH 1/6] PCI: rcar-gen2: Add support for clocks Herve Codina
@ 2022-04-12 15:50 ` Rob Herring
2022-04-13 14:49 ` Herve Codina
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2022-04-12 15:50 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, linux-pci,
linux-renesas-soc, devicetree, linux-kernel, Thomas Petazzoni,
Clement Leger, Miquel Raynal
On Tue, Apr 12, 2022 at 11:40:24AM +0200, Herve Codina wrote:
> The PCI rcar-gen2 does not call any clk_prepare_enable().
> This lead to an access failure when the driver tries to access
> the IP (at least on a RZ/N1D platform).
>
> Prepare and enable clocks using the bulk version of
> clk_prepare_enable() in order to prepare and enable all clocks
> attached to this device.
The binding says there is only a single clock, so it needs an update if
there are multiple clocks. (And ideally converted to DT schema format.)
Rob
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support
2022-04-12 9:40 ` [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support Herve Codina
2022-04-12 10:05 ` Miquel Raynal
@ 2022-04-13 9:08 ` Sergey Shtylyov
2022-04-13 14:59 ` Herve Codina
1 sibling, 1 reply; 12+ messages in thread
From: Sergey Shtylyov @ 2022-04-13 9:08 UTC (permalink / raw)
To: Herve Codina, Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Rob Herring, Krzysztof Kozlowski, Geert Uytterhoeven,
Magnus Damm, Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal
Hello!
On 4/12/22 12:40 PM, Herve Codina wrote:
> Add Renesas R9A06G032 SoC support to the Renesas R-Car gen2 PCI
> bridge driver.
> The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible
> with the one available in the R-Car Gen2 family.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> drivers/pci/controller/pci-rcar-gen2.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
> index 528bc3780e01..586e4785a57f 100644
> --- a/drivers/pci/controller/pci-rcar-gen2.c
> +++ b/drivers/pci/controller/pci-rcar-gen2.c
> @@ -352,6 +352,8 @@ static const struct of_device_id rcar_pci_of_match[] = {
> { .compatible = "renesas,pci-r8a7791", },
> { .compatible = "renesas,pci-r8a7794", },
> { .compatible = "renesas,pci-rcar-gen2", },
> + { .compatible = "renesas,pci-r9a06g032", },
Do we really need this one here? Isn't it covered by the next item?
> + { .compatible = "renesas,pci-rzn1", },
> { },
> };
>
MBR, Sergey
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] PCI: rcar-gen2: Add support for clocks
2022-04-12 15:50 ` Rob Herring
@ 2022-04-13 14:49 ` Herve Codina
0 siblings, 0 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-13 14:49 UTC (permalink / raw)
To: Rob Herring
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, linux-pci,
linux-renesas-soc, devicetree, linux-kernel, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Rob,
On Tue, 12 Apr 2022 10:50:10 -0500
Rob Herring <robh@kernel.org> wrote:
> On Tue, Apr 12, 2022 at 11:40:24AM +0200, Herve Codina wrote:
> > The PCI rcar-gen2 does not call any clk_prepare_enable().
> > This lead to an access failure when the driver tries to access
> > the IP (at least on a RZ/N1D platform).
> >
> > Prepare and enable clocks using the bulk version of
> > clk_prepare_enable() in order to prepare and enable all clocks
> > attached to this device.
>
> The binding says there is only a single clock, so it needs an update if
> there are multiple clocks. (And ideally converted to DT schema format.)
Indeed, I will convert to DT schema format and update the clocks property
description.
Regards,
Hervé
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support
2022-04-13 9:08 ` Sergey Shtylyov
@ 2022-04-13 14:59 ` Herve Codina
0 siblings, 0 replies; 12+ messages in thread
From: Herve Codina @ 2022-04-13 14:59 UTC (permalink / raw)
To: Sergey Shtylyov
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, linux-renesas-soc, devicetree, linux-kernel,
Thomas Petazzoni, Clement Leger, Miquel Raynal
Hi Sergey,
On Wed, 13 Apr 2022 12:08:01 +0300
Sergey Shtylyov <s.shtylyov@omp.ru> wrote:
> Hello!
>
> On 4/12/22 12:40 PM, Herve Codina wrote:
>
> > Add Renesas R9A06G032 SoC support to the Renesas R-Car gen2 PCI
> > bridge driver.
> > The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible
> > with the one available in the R-Car Gen2 family.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> > drivers/pci/controller/pci-rcar-gen2.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
> > index 528bc3780e01..586e4785a57f 100644
> > --- a/drivers/pci/controller/pci-rcar-gen2.c
> > +++ b/drivers/pci/controller/pci-rcar-gen2.c
> > @@ -352,6 +352,8 @@ static const struct of_device_id rcar_pci_of_match[] = {
> > { .compatible = "renesas,pci-r8a7791", },
> > { .compatible = "renesas,pci-r8a7794", },
> > { .compatible = "renesas,pci-rcar-gen2", },
> > + { .compatible = "renesas,pci-r9a06g032", },
>
> Do we really need this one here? Isn't it covered by the next item?
Yes, this one is not needed.
Miquèl did the same remark too.
I will remove '.compatible = "renesas,pci-r9a06g032"' in v2.
Regards,
Herve
>
> > + { .compatible = "renesas,pci-rzn1", },
> > { },
> > };
> >
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-04-13 14:59 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-12 9:40 [PATCH 0/6] RZN1 USB Host support Herve Codina
2022-04-12 9:40 ` [PATCH 1/6] PCI: rcar-gen2: Add support for clocks Herve Codina
2022-04-12 15:50 ` Rob Herring
2022-04-13 14:49 ` Herve Codina
2022-04-12 9:40 ` [PATCH 2/6] dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
2022-04-12 9:40 ` [PATCH 3/6] PCI: rcar-gen2: Add R9A06G032 support Herve Codina
2022-04-12 10:05 ` Miquel Raynal
2022-04-13 9:08 ` Sergey Shtylyov
2022-04-13 14:59 ` Herve Codina
2022-04-12 9:40 ` [PATCH 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
2022-04-12 9:40 ` [PATCH 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
2022-04-12 9:40 ` [PATCH 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
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