From: Serge Semin <fancer.lancer@gmail.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Frank Li" <Frank.Li@nxp.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 20/25] dmaengine: dw-edma: Use non-atomic io-64 methods
Date: Mon, 18 Apr 2022 14:37:13 +0300 [thread overview]
Message-ID: <20220418113713.65xtr4ed2c4gjddl@mobilestation> (raw)
In-Reply-To: <20220325082840.GH4675@thinkpad>
On Fri, Mar 25, 2022 at 01:58:40PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Mar 24, 2022 at 04:48:31AM +0300, Serge Semin wrote:
> > Instead of splitting the 64-bits IOs up into two 32-bits ones it's
> > possible to use an available set of the non-atomic readq/writeq methods
> > implemented exactly for such cases. They are defined in the dedicated
> > header files io-64-nonatomic-lo-hi.h/io-64-nonatomic-hi-lo.h. So in case
> > if the 64-bits readq/writeq methods are unavailable on some platforms at
> > consideration, the corresponding drivers can have any of these headers
> > included and stop locally re-implementing the 64-bits IO accessors taking
> > into account the non-atomic nature of the included methods. Let's do that
> > in the DW eDMA driver too. Note by doing so we can discard the
> > CONFIG_64BIT config ifdefs from the code. Also note that if a platform
> > doesn't support 64-bit DBI IOs then the corresponding accessors will just
> > directly call the lo_hi_readq()/lo_hi_writeq() methods.
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > ---
> > drivers/dma/dw-edma/dw-edma-v0-core.c | 71 +++++++++------------------
> > 1 file changed, 24 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> > index 6b303d5a6b2a..ebb860e19c75 100644
> > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> > @@ -8,6 +8,8 @@
> >
> > #include <linux/bitfield.h>
> >
> > +#include <linux/io-64-nonatomic-lo-hi.h>
> > +
> > #include "dw-edma-core.h"
> > #include "dw-edma-v0-core.h"
> > #include "dw-edma-v0-regs.h"
> > @@ -53,8 +55,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
> > SET_32(dw, rd_##name, value); \
> > } while (0)
> >
> > -#ifdef CONFIG_64BIT
> > -
> > #define SET_64(dw, name, value) \
> > writeq(value, &(__dw_regs(dw)->name))
> >
> > @@ -80,8 +80,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
> > SET_64(dw, rd_##name, value); \
> > } while (0)
> >
> > -#endif /* CONFIG_64BIT */
> > -
> > #define SET_COMPAT(dw, name, value) \
> > writel(value, &(__dw_regs(dw)->type.unroll.name))
> >
> > @@ -164,14 +162,13 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
> > #define SET_LL_32(ll, value) \
> > writel(value, ll)
> >
> > -#ifdef CONFIG_64BIT
> > -
> > static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
> > u64 value, void __iomem *addr)
> > {
> > + unsigned long flags;
> > +
> > if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
> > u32 viewport_sel;
> > - unsigned long flags;
> >
> > raw_spin_lock_irqsave(&dw->lock, flags);
> >
> > @@ -181,22 +178,25 @@ static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
> >
> > writel(viewport_sel,
> > &(__dw_regs(dw)->type.legacy.viewport_sel));
> > + }
> > +
> > + if (dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI)
> > + lo_hi_writeq(value, addr);
> > + else
> > writeq(value, addr);
> >
> > + if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)
> > raw_spin_unlock_irqrestore(&dw->lock, flags);
> > - } else {
> > - writeq(value, addr);
> > - }
> > }
> >
> > static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
> > const void __iomem *addr)
> > {
> > - u32 value;
> > + unsigned long flags;
> > + u64 value;
> >
> > if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
> > u32 viewport_sel;
> > - unsigned long flags;
> >
> > raw_spin_lock_irqsave(&dw->lock, flags);
> >
> > @@ -206,12 +206,15 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
> >
> > writel(viewport_sel,
> > &(__dw_regs(dw)->type.legacy.viewport_sel));
> > + }
> > +
> > + if (dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI)
> > + value = lo_hi_readq(addr);
> > + else
> > value = readq(addr);
> >
> > + if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)
> > raw_spin_unlock_irqrestore(&dw->lock, flags);
> > - } else {
> > - value = readq(addr);
> > - }
> >
> > return value;
> > }
> > @@ -225,8 +228,6 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
> > #define SET_LL_64(ll, value) \
> > writeq(value, ll)
> >
> > -#endif /* CONFIG_64BIT */
> > -
> > /* eDMA management callbacks */
> > void dw_edma_v0_core_off(struct dw_edma *dw)
> > {
> > @@ -325,19 +326,10 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
> > /* Transfer size */
> > SET_LL_32(&lli[i].transfer_size, child->sz);
> > /* SAR */
> > - #ifdef CONFIG_64BIT
> > - SET_LL_64(&lli[i].sar.reg, child->sar);
> > - #else /* CONFIG_64BIT */
> > - SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar));
> > - SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar));
> > - #endif /* CONFIG_64BIT */
> > + SET_LL_64(&lli[i].sar.reg, child->sar);
>
> This macro still uses writeq(), that's not available on 32bit platforms.
> Am I missing anything?
Yes, the writeq/readq macro are defined in the
include/linux/{io-64-nonatomic-lo-hi.h,io-64-nonatomic-hi-lo.h} files.
If the platform doesn't provide its own 64-bit IOs implementation
these macro are used and are unwrapped with the two writel/readl
methods.
-Sergey
>
> Thanks,
> Mani
>
> > /* DAR */
> > - #ifdef CONFIG_64BIT
> > - SET_LL_64(&lli[i].dar.reg, child->dar);
> > - #else /* CONFIG_64BIT */
> > - SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar));
> > - SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar));
> > - #endif /* CONFIG_64BIT */
> > + SET_LL_64(&lli[i].dar.reg, child->dar);
> > +
> > i++;
> > }
> >
> > @@ -349,12 +341,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
> > /* Channel control */
> > SET_LL_32(&llp->control, control);
> > /* Linked list */
> > - #ifdef CONFIG_64BIT
> > - SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
> > - #else /* CONFIG_64BIT */
> > - SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr));
> > - SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr));
> > - #endif /* CONFIG_64BIT */
> > + SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
> > }
> >
> > void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> > @@ -417,18 +404,8 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> > SET_CH_32(dw, chan->dir, chan->id, ch_control1,
> > (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
> > /* Linked list */
> > - if ((chan->dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI) ||
> > - !IS_ENABLED(CONFIG_64BIT)) {
> > - SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
> > - lower_32_bits(chunk->ll_region.paddr));
> > - SET_CH_32(dw, chan->dir, chan->id, llp.msb,
> > - upper_32_bits(chunk->ll_region.paddr));
> > - } else {
> > - #ifdef CONFIG_64BIT
> > - SET_CH_64(dw, chan->dir, chan->id, llp.reg,
> > - chunk->ll_region.paddr);
> > - #endif
> > - }
> > + SET_CH_64(dw, chan->dir, chan->id, llp.reg,
> > + chunk->ll_region.paddr);
> > }
> > /* Doorbell */
> > SET_RW_32(dw, chan->dir, doorbell,
> > --
> > 2.35.1
> >
next prev parent reply other threads:[~2022-04-18 11:37 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 1:48 [PATCH 00/25] dmaengine: dw-edma: Add RP/EP local DMA controllers support Serge Semin
2022-03-24 1:48 ` [PATCH 01/25] dmaengine: dw-edma: Drop dma_slave_config.direction field usage Serge Semin
2022-03-24 13:30 ` Manivannan Sadhasivam
2022-04-05 11:15 ` Serge Semin
2022-03-24 1:48 ` [PATCH 02/25] dmaengine: dw-edma: Fix eDMA Rd/Wr-channels and DMA-direction semantics Serge Semin
2022-03-24 1:48 ` [PATCH 03/25] dma-direct: take dma-ranges/offsets into account in resource mapping Serge Semin
2022-03-24 11:30 ` Robin Murphy
2022-04-17 22:44 ` Serge Semin
2022-04-20 7:12 ` Christoph Hellwig
2022-04-20 8:32 ` Serge Semin
2022-04-20 8:47 ` Christoph Hellwig
2022-04-20 8:55 ` Serge Semin
2022-04-21 14:45 ` Christoph Hellwig
2022-04-21 17:35 ` Serge Semin
2022-04-21 20:51 ` Robin Murphy
2022-04-24 21:46 ` Serge Semin
2022-03-24 1:48 ` [PATCH 04/25] dmaengine: Fix dma_slave_config.dst_addr description Serge Semin
2022-03-24 14:08 ` Manivannan Sadhasivam
2022-03-31 5:38 ` Vinod Koul
2022-03-31 7:13 ` Serge Semin
2022-03-31 10:50 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 05/25] dmaengine: dw-edma: Convert ll/dt phys-address to PCIe bus/DMA address Serge Semin
2022-03-24 16:23 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 06/25] dmaengine: dw-edma: Fix missing src/dst address of the interleaved xfers Serge Semin
2022-03-24 16:26 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 07/25] dmaengine: dw-edma: Don't permit non-inc " Serge Semin
2022-03-24 17:15 ` Manivannan Sadhasivam
2022-04-17 22:59 ` Serge Semin
2022-03-24 1:48 ` [PATCH 08/25] dmaengine: dw-edma: Fix invalid interleaved xfers semantics Serge Semin
2022-03-24 1:48 ` [PATCH 09/25] dmaengine: dw-edma: Add CPU to PCIe bus address translation Serge Semin
2022-03-24 17:25 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 10/25] dmaengine: dw-edma: Add PCIe bus address getter to the remote EP glue-driver Serge Semin
2022-03-24 17:41 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 11/25] dmaengine: dw-edma: Drop chancnt initialization Serge Semin
2022-03-24 17:42 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 12/25] dmaengine: dw-edma: Fix DebugFS reg entry type Serge Semin
2022-03-24 17:48 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 13/25] dmaengine: dw-edma: Stop checking debugfs_create_*() return value Serge Semin
2022-03-24 18:12 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 14/25] dmaengine: dw-edma: Add dw_edma prefix to the DebugFS nodes descriptor Serge Semin
2022-03-24 18:14 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 15/25] dmaengine: dw-edma: Convert DebugFS descs to being kz-allocated Serge Semin
2022-03-25 6:03 ` Manivannan Sadhasivam
2022-03-25 6:42 ` Manivannan Sadhasivam
2022-04-18 7:17 ` Serge Semin
2022-03-24 1:48 ` [PATCH 16/25] dmaengine: dw-edma: Simplify the DebugFS context CSRs init procedure Serge Semin
2022-03-25 6:27 ` Manivannan Sadhasivam
2022-03-25 6:31 ` Manivannan Sadhasivam
2022-04-18 8:23 ` Serge Semin
2022-03-24 1:48 ` [PATCH 17/25] dmaengine: dw-edma: Move eDMA data pointer to DebugFS node descriptor Serge Semin
2022-03-25 6:35 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 18/25] dmaengine: dw-edma: Join Write/Read channels into a single device Serge Semin
2022-03-25 7:34 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 19/25] dmaengine: dw-edma: Use DMA-engine device DebugFS subdirectory Serge Semin
2022-03-25 7:41 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 20/25] dmaengine: dw-edma: Use non-atomic io-64 methods Serge Semin
2022-03-25 8:28 ` Manivannan Sadhasivam
2022-04-18 11:37 ` Serge Semin [this message]
2022-03-24 1:48 ` [PATCH 21/25] dmaengine: dw-edma: Drop DT-region allocation Serge Semin
2022-03-25 8:33 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 22/25] dmaengine: dw-edma: Replace chip ID number with device name Serge Semin
2022-03-25 10:02 ` Manivannan Sadhasivam
2022-04-18 12:17 ` Serge Semin
2022-03-24 1:48 ` [PATCH 23/25] dmaengine: dw-edma: Bypass dma-ranges mapping for the local setup Serge Semin
2022-03-25 18:10 ` Manivannan Sadhasivam
2022-04-18 13:36 ` Serge Semin
2022-03-24 1:48 ` [PATCH 24/25] dmaengine: dw-edma: Skip cleanup procedure if no private data found Serge Semin
2022-03-25 18:15 ` Manivannan Sadhasivam
2022-04-18 13:48 ` Serge Semin
2022-04-23 14:45 ` Manivannan Sadhasivam
2022-03-24 1:48 ` [PATCH 25/25] PCI: dwc: Add DW eDMA engine support Serge Semin
2022-03-28 14:15 ` Manivannan Sadhasivam
2022-04-19 20:54 ` Serge Semin
2022-04-23 14:40 ` Manivannan Sadhasivam
2022-04-25 5:22 ` Manivannan Sadhasivam
2022-04-28 14:05 ` Serge Semin
2022-04-28 17:09 ` Manivannan Sadhasivam
2022-04-29 16:13 ` Serge Semin
2022-04-29 17:20 ` Manivannan Sadhasivam
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