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From: Bjorn Helgaas <helgaas@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Conor.Dooley@microchip.com, lorenzo.pieralisi@arm.com,
	Daire.McNamara@microchip.com, bhelgaas@google.com,
	Cyril.Jean@microchip.com, david.abdurachmanov@gmail.com,
	linux-pci@vger.kernel.org, robh@kernel.org
Subject: Re: [RESEND PATCH v1 1/1] PCI: microchip: Fix potential race in interrupt handling
Date: Mon, 2 May 2022 14:22:23 -0500	[thread overview]
Message-ID: <20220502192223.GA319570@bhelgaas> (raw)
In-Reply-To: <87h76b8nxc.wl-maz@kernel.org>

On Sat, Apr 30, 2022 at 12:33:51AM +0100, Marc Zyngier wrote:
> On Fri, 29 Apr 2022 22:57:33 +0100,
> Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Fri, Apr 29, 2022 at 09:42:52AM +0000, Conor.Dooley@microchip.com wrote:
> > > On 28/04/2022 10:29, Lorenzo Pieralisi wrote:
> > > > On Tue, Apr 05, 2022 at 12:17:51PM +0100, daire.mcnamara@microchip.com wrote:
> > > >> From: Daire McNamara <daire.mcnamara@microchip.com>
> > > >>
> > > >> Clear MSI bit in ISTATUS register after reading it before
> > > >> handling individual MSI bits

> > > Clear the MSI bit in ISTATUS register after reading it, but before
> > > reading and handling individual MSI bits from the IMSI register.
> > > This avoids a potential race where new MSI bits may be set on the
> > > IMSI register after it was read and be missed when the MSI bit in
> > > the ISTATUS register is cleared.

> > Honestly, I don't understand enough about IRQs to determine whether
> > this is a correct fix.  Hopefully Marc will chime in.  All I really
> > know how to do is compare all the drivers and see which ones don't fit
> > the typical patterns.
> 
> This seems sensible. In general, edge interrupts need an early Ack
> *before* the handler can be run. If it happens after, you're pretty
> much guaranteed to lose edges that would be generated between the
> handler and the late Ack.
> 
> This can be implemented in HW in a variety of ways (read a register,
> write a register, or even both).

Is this something that is or could be documented somewhere under
Documentation, e.g., "here are the common canonical patterns to use"?
I feel like an idiot because I have this kind of question all the time
and I never know how to confidently analyze it.

> > And speaking of that, I looked at all the users of
> > irq_set_chained_handler_and_data() in drivers/pci.  All the handlers
> > except mc_handle_intx() and mc_handle_msi() call chained_irq_enter()
> > and chained_irq_exit().
> > 
> > Are mc_handle_intx() and mc_handle_msi() just really special, or is
> > this a mistake?
> 
> That's just a bug. On the right HW, this would just result in lost
> interrupts.

I wonder if coccinelle or some other static analyzer would be smart
enough to find this kind of error.

Bjorn

  reply	other threads:[~2022-05-02 19:22 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-05 11:17 [RESEND PATCH v1 1/1] PCI: microchip: Fix potential race in interrupt handling daire.mcnamara
2022-04-28  6:30 ` Conor.Dooley
2022-04-28  9:29 ` Lorenzo Pieralisi
2022-04-29  9:42   ` Conor.Dooley
2022-04-29 21:57     ` Bjorn Helgaas
2022-04-29 23:33       ` Marc Zyngier
2022-05-02 19:22         ` Bjorn Helgaas [this message]
2022-05-04 15:12           ` Conor Dooley
2022-05-04 16:53             ` Lorenzo Pieralisi
2022-05-04 16:57               ` Conor Dooley
2022-05-04 16:59             ` Bjorn Helgaas
2022-05-11 10:00               ` Conor Dooley
2022-05-11 12:41                 ` Lorenzo Pieralisi

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