Re: [RESEND PATCH v1 1/1] PCI: microchip: Fix potential race in interrupt handling

From: Marc Zyngier <maz@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Conor.Dooley@microchip.com, lorenzo.pieralisi@arm.com,
	Daire.McNamara@microchip.com, bhelgaas@google.com,
	Cyril.Jean@microchip.com, david.abdurachmanov@gmail.com,
	linux-pci@vger.kernel.org, robh@kernel.org
Subject: Re: [RESEND PATCH v1 1/1] PCI: microchip: Fix potential race in interrupt handling
Date: Sat, 30 Apr 2022 00:33:51 +0100	[thread overview]
Message-ID: <87h76b8nxc.wl-maz@kernel.org> (raw)
In-Reply-To: <20220429215733.GA97739@bhelgaas>

On Fri, 29 Apr 2022 22:57:33 +0100,
Bjorn Helgaas <helgaas@kernel.org> wrote:
> 
> [+to Marc]
> 
> On Fri, Apr 29, 2022 at 09:42:52AM +0000, Conor.Dooley@microchip.com wrote:
> > On 28/04/2022 10:29, Lorenzo Pieralisi wrote:
> > > On Tue, Apr 05, 2022 at 12:17:51PM +0100, daire.mcnamara@microchip.com wrote:
> > >> From: Daire McNamara <daire.mcnamara@microchip.com>
> > >>
> > >> Clear MSI bit in ISTATUS register after reading it before
> > >> handling individual MSI bits
> > > 
> > > That explains nothing. If you are fixing a bug please describe
> > > the issue and how the patch is fixing it.
> > 
> > Someone in the pantheon of IT gods has it out for Daire, so I am
> > sending this on his behalf, but is the following revised commit
> > message better?
> > 
> > Clear the MSI bit in ISTATUS register after reading it, but before
> > reading and handling individual MSI bits from the IMSI register.
> > This avoids a potential race where new MSI bits may be set on the
> > IMSI register after it was read and be missed when the MSI bit in
> > the ISTATUS register is cleared.
> 
> "ISTATUS" doesn't appear in the code as a register name.  Neither does
> "IMSI".  Please use names that match the code.
> 
> Honestly, I don't understand enough about IRQs to determine whether
> this is a correct fix.  Hopefully Marc will chime in.  All I really
> know how to do is compare all the drivers and see which ones don't fit
> the typical patterns.

This seems sensible. In general, edge interrupts need an early Ack
*before* the handler can be run. If it happens after, you're pretty
much guaranteed to lose edges that would be generated between the
handler and the late Ack.

This can be implemented in HW in a variety of ways (read a register,
write a register, or even both).

> 
> And speaking of that, I looked at all the users of
> irq_set_chained_handler_and_data() in drivers/pci.  All the handlers
> except mc_handle_intx() and mc_handle_msi() call chained_irq_enter()
> and chained_irq_exit().
> 
> Are mc_handle_intx() and mc_handle_msi() just really special, or is
> this a mistake?

That's just a bug. On the right HW, this would just result in lost
interrupts.

	M.

-- 
Without deviation from the norm, progress is not possible.