From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<michals@xilinx.com>, <robh@kernel.org>,
Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v4 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
Date: Wed, 8 Jun 2022 22:10:45 +0530 [thread overview]
Message-ID: <20220608164046.3474-2-bharat.kumar.gogada@xilinx.com> (raw)
In-Reply-To: <20220608164046.3474-1-bharat.kumar.gogada@xilinx.com>
Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.
Add support for YAML schemas documentation for Versal CPM5 Root Port driver.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
.../bindings/pci/xilinx-versal-cpm.yaml | 48 +++++++++++++++++--
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index cca395317a4c..80597f2974e5 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -14,17 +14,27 @@ allOf:
properties:
compatible:
- const: xlnx,versal-cpm-host-1.00
+ contains:
+ enum:
+ - xlnx,versal-cpm-host-1.00
+ - xlnx,versal-cpm5-host
reg:
items:
- description: CPM system level control and status registers.
- description: Configuration space region and bridge registers.
+ - description: CPM5 control and status registers.
+ minItems: 2
reg-names:
- items:
- - const: cpm_slcr
- - const: cfg
+ oneOf:
+ - items:
+ - const: cpm_slcr
+ - const: cfg
+ - items:
+ - const: cpm_slcr
+ - const: cfg
+ - const: cpm_csr
interrupts:
maxItems: 1
@@ -95,4 +105,34 @@ examples:
interrupt-controller;
};
};
+
+ cpm5_pcie: pcie@fcdd0000 {
+ compatible = "xlnx,versal-cpm5-host";
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <0 72 4>;
+ interrupt-parent = <&gic>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
+ <0 0 0 2 &pcie_intc_1 1>,
+ <0 0 0 3 &pcie_intc_1 2>,
+ <0 0 0 4 &pcie_intc_1 3>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+ <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
+ msi-map = <0x0 &its_gic 0x0 0x10000>;
+ reg = <0x00 0xfcdd0000 0x00 0x1000>,
+ <0x06 0x00000000 0x00 0x1000000>,
+ <0x00 0xfce20000 0x00 0x1000000>;
+ reg-names = "cpm_slcr", "cfg", "cpm_csr";
+
+ pcie_intc_1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
};
--
2.17.1
next prev parent reply other threads:[~2022-06-08 16:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-08 16:40 [PATCH v4 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
2022-06-08 16:40 ` Bharat Kumar Gogada [this message]
2022-06-09 21:10 ` [PATCH v4 1/2] dt-bindings: PCI: xilinx-cpm: Add " Rob Herring
2022-06-10 8:50 ` Bharat Kumar Gogada
2022-06-08 16:40 ` [PATCH v4 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
2022-06-08 19:14 ` Bjorn Helgaas
2022-06-09 7:59 ` Michal Simek
2022-06-09 17:32 ` Bjorn Helgaas
2022-06-10 8:49 ` Bharat Kumar Gogada
2022-06-10 8:47 ` Bharat Kumar Gogada
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