* Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
2022-06-02 1:55 ` [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers Palmer Dabbelt
@ 2022-06-02 4:39 ` Conor.Dooley
2022-06-02 16:31 ` Bjorn Helgaas
2022-06-02 16:03 ` Bjorn Helgaas
2022-06-09 22:43 ` Stephen Boyd
2 siblings, 1 reply; 7+ messages in thread
From: Conor.Dooley @ 2022-06-02 4:39 UTC (permalink / raw)
To: palmer, gregkh, arnd, akpm
Cc: sboyd, linux-pci, mturquette, paul.walmsley, kw, linux-clk, aou,
lorenzo.pieralisi, linux-kernel, linux-riscv, Daire.McNamara,
Lewis.Hanly, Cyril.Jean, robh
On 02/06/2022 02:55, Palmer Dabbelt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, 23 May 2022 13:00:01 PDT (-0700), Conor.Dooley@microchip.com wrote:
>> On 23/05/2022 20:52, Palmer Dabbelt wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley@microchip.com wrote:
>>>> On 05/05/2022 11:55, Conor Dooley wrote:
>>>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
>>>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
>>>>> Daire is the author of the clock & PCI drivers, so add him as a
>>>>> maintainer in place of Lewis.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> Hey Palmer,
>>>> I know youre busy etc but just a reminder :)
>>>
>>> Sorry, I didn't realize this was aimed at the RISC-V tree. I'm fine
>>> taking it, but it seems like these should have gone in along with the
>>> drivers.
>>
>> Yeah, sorry. In hindsight it should've but that ship has sailed. I sent
>> the rng bundled this way b/c I didn't want to end up a conflict.
>> Obv. there's not a rush so I can always split it back out if needs be.
>
> I'm adding a bunch of subsystem maintainers just to check again. I
> don't have any problem with it, just not really a RISC-V thing and don't
> wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
> for now.
>
> Sorry if I'm being overly pedantic about this one...
I don't mind. Maybe this should go via Andrew next cycle or w/e?
There's obviously no hurry etc
>
>>
>>>
>>> Arnd: maybe this is really an SOC tree sort of thing? No big deal
>>> either way on my end, just let me know.
>>>
>>>> Thanks,
>>>> Conor.
>>>>
>>>>> ---
>>>>> MAINTAINERS | 5 ++++-
>>>>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>>> index fd768d43e048..d7602658b0a5 100644
>>>>> --- a/MAINTAINERS
>>>>> +++ b/MAINTAINERS
>>>>> @@ -16939,12 +16939,15 @@ N: riscv
>>>>> K: riscv
>>>>>
>>>>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>>>>> -M: Lewis Hanly <lewis.hanly@microchip.com>
>>>>> M: Conor Dooley <conor.dooley@microchip.com>
>>>>> +M: Daire McNamara <daire.mcnamara@microchip.com>
>>>>> L: linux-riscv@lists.infradead.org
>>>>> S: Supported
>>>>> F: arch/riscv/boot/dts/microchip/
>>>>> +F: drivers/char/hw_random/mpfs-rng.c
>>>>> +F: drivers/clk/microchip/clk-mpfs.c
>>>>> F: drivers/mailbox/mailbox-mpfs.c
>>>>> +F: drivers/pci/controller/pcie-microchip-host.c
>>>>> F: drivers/soc/microchip/
>>>>> F: include/soc/microchip/mpfs.h
>>>>>
>>>>
>>
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
2022-06-02 4:39 ` Conor.Dooley
@ 2022-06-02 16:31 ` Bjorn Helgaas
2022-06-02 22:05 ` Palmer Dabbelt
0 siblings, 1 reply; 7+ messages in thread
From: Bjorn Helgaas @ 2022-06-02 16:31 UTC (permalink / raw)
To: Conor.Dooley
Cc: palmer, gregkh, arnd, akpm, sboyd, linux-pci, mturquette,
paul.walmsley, kw, linux-clk, aou, lorenzo.pieralisi,
linux-kernel, linux-riscv, Daire.McNamara, Lewis.Hanly,
Cyril.Jean, robh
On Thu, Jun 02, 2022 at 04:39:08AM +0000, Conor.Dooley@microchip.com wrote:
> On 02/06/2022 02:55, Palmer Dabbelt wrote:
> > I'm adding a bunch of subsystem maintainers just to check again. I
> > don't have any problem with it, just not really a RISC-V thing and don't
> > wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
> > for now.
> >
> > Sorry if I'm being overly pedantic about this one...
>
> I don't mind. Maybe this should go via Andrew next cycle or w/e?
> There's obviously no hurry etc
My turn to be overly pedantic :) IMHO there's no benefit in delaying
MAINTAINERS updates. There's zero risk, and delaying only means
people will miss out on bug reports and other things they should learn
about.
Bjorn
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
2022-06-02 16:31 ` Bjorn Helgaas
@ 2022-06-02 22:05 ` Palmer Dabbelt
0 siblings, 0 replies; 7+ messages in thread
From: Palmer Dabbelt @ 2022-06-02 22:05 UTC (permalink / raw)
To: helgaas
Cc: Conor.Dooley, Greg KH, Arnd Bergmann, akpm, sboyd, linux-pci,
mturquette, Paul Walmsley, kw, linux-clk, aou, lorenzo.pieralisi,
linux-kernel, linux-riscv, Daire.McNamara, Lewis.Hanly,
Cyril.Jean, robh
On Thu, 02 Jun 2022 09:31:52 PDT (-0700), helgaas@kernel.org wrote:
> On Thu, Jun 02, 2022 at 04:39:08AM +0000, Conor.Dooley@microchip.com wrote:
>> On 02/06/2022 02:55, Palmer Dabbelt wrote:
>
>> > I'm adding a bunch of subsystem maintainers just to check again. I
>> > don't have any problem with it, just not really a RISC-V thing and don't
>> > wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
>> > for now.
>> >
>> > Sorry if I'm being overly pedantic about this one...
>>
>> I don't mind. Maybe this should go via Andrew next cycle or w/e?
>> There's obviously no hurry etc
>
> My turn to be overly pedantic :) IMHO there's no benefit in delaying
> MAINTAINERS updates. There's zero risk, and delaying only means
> people will miss out on bug reports and other things they should learn
> about.
If by "delay" you mean wait until a merge window, then I definately
agree -- that's just more cofusing for folks to have defacto
maintainership outside of the tree, might as well get these in. It's
not like a MAINTAINERS update is going to introduce a regression or
anything.
I'm just delaying because I just want to wait to make sure folks from
the subsystems are OK with the updates, as these aren't really anything
to do with RISC-V so it's not really my decision to make.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
2022-06-02 1:55 ` [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers Palmer Dabbelt
2022-06-02 4:39 ` Conor.Dooley
@ 2022-06-02 16:03 ` Bjorn Helgaas
2022-06-09 22:43 ` Stephen Boyd
2 siblings, 0 replies; 7+ messages in thread
From: Bjorn Helgaas @ 2022-06-02 16:03 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Conor.Dooley, Greg KH, Arnd Bergmann, mturquette, sboyd,
linux-clk, lorenzo.pieralisi, robh, kw, linux-pci, Paul Walmsley,
aou, linux-kernel, linux-riscv, Daire.McNamara, Lewis.Hanly,
Cyril.Jean
On Wed, Jun 01, 2022 at 06:55:40PM -0700, Palmer Dabbelt wrote:
> On Mon, 23 May 2022 13:00:01 PDT (-0700), Conor.Dooley@microchip.com wrote:
> > On 23/05/2022 20:52, Palmer Dabbelt wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley@microchip.com wrote:
> >>> On 05/05/2022 11:55, Conor Dooley wrote:
> >>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
> >>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
> >>>> Daire is the author of the clock & PCI drivers, so add him as a
> >>>> maintainer in place of Lewis.
> >>>>
> >>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> Hey Palmer,
> >>> I know youre busy etc but just a reminder :)
> >>
> >> Sorry, I didn't realize this was aimed at the RISC-V tree. I'm fine
> >> taking it, but it seems like these should have gone in along with the
> >> drivers.
> >
> > Yeah, sorry. In hindsight it should've but that ship has sailed. I sent
> > the rng bundled this way b/c I didn't want to end up a conflict.
> > Obv. there's not a rush so I can always split it back out if needs be.
>
> I'm adding a bunch of subsystem maintainers just to check again. I
> don't have any problem with it, just not really a RISC-V thing and don't
> wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
> for now.
Fine with me, if you want it:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> >> Arnd: maybe this is really an SOC tree sort of thing? No big deal
> >> either way on my end, just let me know.
> >>
> >>> Thanks,
> >>> Conor.
> >>>
> >>>> ---
> >>>> MAINTAINERS | 5 ++++-
> >>>> 1 file changed, 4 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/MAINTAINERS b/MAINTAINERS
> >>>> index fd768d43e048..d7602658b0a5 100644
> >>>> --- a/MAINTAINERS
> >>>> +++ b/MAINTAINERS
> >>>> @@ -16939,12 +16939,15 @@ N: riscv
> >>>> K: riscv
> >>>>
> >>>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> >>>> -M: Lewis Hanly <lewis.hanly@microchip.com>
> >>>> M: Conor Dooley <conor.dooley@microchip.com>
> >>>> +M: Daire McNamara <daire.mcnamara@microchip.com>
> >>>> L: linux-riscv@lists.infradead.org
> >>>> S: Supported
> >>>> F: arch/riscv/boot/dts/microchip/
> >>>> +F: drivers/char/hw_random/mpfs-rng.c
> >>>> +F: drivers/clk/microchip/clk-mpfs.c
> >>>> F: drivers/mailbox/mailbox-mpfs.c
> >>>> +F: drivers/pci/controller/pcie-microchip-host.c
> >>>> F: drivers/soc/microchip/
> >>>> F: include/soc/microchip/mpfs.h
> >>>>
> >>>
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
2022-06-02 1:55 ` [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers Palmer Dabbelt
2022-06-02 4:39 ` Conor.Dooley
2022-06-02 16:03 ` Bjorn Helgaas
@ 2022-06-09 22:43 ` Stephen Boyd
2022-06-09 22:53 ` Conor.Dooley
2 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2022-06-09 22:43 UTC (permalink / raw)
To: Arnd Bergmann, Conor.Dooley, Greg KH, Palmer Dabbelt, kw,
linux-clk, linux-pci, lorenzo.pieralisi, mturquette, robh
Cc: Arnd Bergmann, Paul Walmsley, aou, linux-kernel, linux-riscv,
Daire.McNamara, Lewis.Hanly, Cyril.Jean
Quoting Palmer Dabbelt (2022-06-01 18:55:40)
> On Mon, 23 May 2022 13:00:01 PDT (-0700), Conor.Dooley@microchip.com wrote:
> > On 23/05/2022 20:52, Palmer Dabbelt wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley@microchip.com wrote:
> >>> On 05/05/2022 11:55, Conor Dooley wrote:
> >>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
> >>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
> >>>> Daire is the author of the clock & PCI drivers, so add him as a
> >>>> maintainer in place of Lewis.
> >>>>
> >>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> Hey Palmer,
> >>> I know youre busy etc but just a reminder :)
> >>
> >> Sorry, I didn't realize this was aimed at the RISC-V tree.�� I'm fine
> >> taking it, but it seems like these should have gone in along with the
> >> drivers.
> >
> > Yeah, sorry. In hindsight it should've but that ship has sailed. I sent
> > the rng bundled this way b/c I didn't want to end up a conflict.
> > Obv. there's not a rush so I can always split it back out if needs be.
>
> I'm adding a bunch of subsystem maintainers just to check again. I
> don't have any problem with it, just not really a RISC-V thing and don't
> wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
> for now.
>
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
2022-06-09 22:43 ` Stephen Boyd
@ 2022-06-09 22:53 ` Conor.Dooley
0 siblings, 0 replies; 7+ messages in thread
From: Conor.Dooley @ 2022-06-09 22:53 UTC (permalink / raw)
To: sboyd, arnd, Conor.Dooley, gregkh, palmer, kw, linux-clk,
linux-pci, lorenzo.pieralisi, mturquette, robh, herbert
Cc: paul.walmsley, aou, linux-kernel, linux-riscv, Daire.McNamara,
Cyril.Jean
On 09/06/2022 23:43, Stephen Boyd wrote:
> Quoting Palmer Dabbelt (2022-06-01 18:55:40)
>> On Mon, 23 May 2022 13:00:01 PDT (-0700), Conor.Dooley@microchip.com wrote:
>>> On 23/05/2022 20:52, Palmer Dabbelt wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley@microchip.com wrote:
>>>>> On 05/05/2022 11:55, Conor Dooley wrote:
>>>>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
>>>>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
>>>>>> Daire is the author of the clock & PCI drivers, so add him as a
>>>>>> maintainer in place of Lewis.
>>>>>>
>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> Hey Palmer,
>>>>> I know youre busy etc but just a reminder :)
>>>>
>>>> Sorry, I didn't realize this was aimed at the RISC-V tree.�� I'm fine
>>>> taking it, but it seems like these should have gone in along with the
>>>> drivers.
>>>
>>> Yeah, sorry. In hindsight it should've but that ship has sailed. I sent
>>> the rng bundled this way b/c I didn't want to end up a conflict.
>>> Obv. there's not a rush so I can always split it back out if needs be.
>>
>> I'm adding a bunch of subsystem maintainers just to check again. I
>> don't have any problem with it, just not really a RISC-V thing and don't
>> wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
>> for now.
>>
>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
>
+CC Herbert for the last one.
This is likely to generate a conflict in -next though b/c
my spi driver that was applied for 5.20 also touches this
entry. It really pisses me off that I allowed this to
happen & become a burden..
What am I "meant" to do here? Do the merges myself & provide
the conflict resolution? Or for something as obvious as this
is it enough to notify that there will be one?
Sorry,
Conor.
^ permalink raw reply [flat|nested] 7+ messages in thread