From: Wangseok Lee <wangseok.lee@samsung.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"kishon@ti.com" <kishon@ti.com>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
"lars.persson@axis.com" <lars.persson@axis.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"kw@linux.com" <kw@linux.com>,
"linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>,
"kernel@axis.com" <kernel@axis.com>,
Moon-Ki Jun <moonki.jun@samsung.com>,
Sang Min Kim <hypmean.kim@samsung.com>,
Dongjin Yang <dj76.yang@samsung.com>,
Yeeun Kim <yeeun119.kim@samsung.com>
Subject: Re: [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
Date: Wed, 22 Jun 2022 16:06:25 +0900 [thread overview]
Message-ID: <20220622070625epcms2p27b8af447c871dba8219b5dd16c2860c7@epcms2p2> (raw)
In-Reply-To: <20220621211354.GA1332400@bhelgaas>
On 22/06/2022 06:23, Bjorn Helgaas wrote:
> On Mon, Jun 20, 2022 at 05:38:21PM +0900, Wangseok Lee wrote:
>> On 17/06/2022 07:59, Krzysztof Kozlowski wrote:
>> > On 13/06/2022 18:29, Wangseok Lee wrote:
>> >> Add description to support Axis, ARTPEC-8 SoC.
>> >> ARTPEC-8 is the SoC platform of Axis Communications
>> >> and PCIe phy is designed based on SAMSUNG PHY.
>> >
>> > No improvements here. On v2 I gave you link pointing to specific
>> > paragraph of our documentation which you need to apply - wrong wrapping.
>> > Is there something unclear here?
>> >
>> > Please
>> > do
>> > not
>> > wrap
>> > in
>> > different
>> > style.
>>
>> I think i misunderstood your review comment.
>
> Krzysztof was pointing out that your commit log:
>
> Add description to support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications
> and PCIe phy is designed based on SAMSUNG PHY.
>
> only fills about 50 columns, and if you run "git log", most commit logs
> fill about 75 columns so that when git adds 4 spaces of indentation, they
> fit nicely in an 80-column terminal and take advantage of the whole width.
>
> It's easier to read when all the commit logs are roughly the same
> width. So please wrap yours to something like this:
>
> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC
> platform of Axis Communications and PCIe PHY is designed based on Samsung
> PHY.
>
> The PCI driver the commit log is:
>
> Add support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications.
>
> This is based on arm64 and support GEN4 & 2lane.
> This PCIe controller is based on DesignWare Hardware core and uses DesignWa
> re core functions to implement the driver.
>
> "pcie-artpec6. c" supports artpec6 and artpec7 H/W.
> artpec8 can not be expanded because H/W configuration is completely differe
> nt from artpec6/7.
> phy and sub controller are different.
>
> This should be similarly rewrapped to fill 75 columns. The short lines are
> a signal to the reader that "this is the last line of a paragraph, so
> expect a new paragraph to follow."
>
> But in commit logs, paragraphs are typically separated by blank lines, so a
> short line followed not by a blank line but by text that *could* fit on the
> previous short line is a confusing signal.
>
> This similar to the Wikipedia style:
> https://en.wikipedia.org/wiki/Wikipedia:Manual_of_Style/Layout#Paragraphs
>
> The PCI driver commit log should also join "DesignWare" and "different",
> which are currently split across lines.
>
>> I will modify it as below.
>> s/SAMSUNG PHY/Samsung phy
>
> "PHY" is typically all caps in English text, e.g., see examples here:
> https://en.wikipedia.org/wiki/Physical_layer#PHY
>
> Bjorn
Thank you very much for your detailed review.
I will fix the commit msgs as your description.
Best regards,
Wangseok Lee
next prev parent reply other threads:[~2022-06-22 7:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7>
2022-06-14 1:16 ` [PATCH v3 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p3>
2022-06-14 1:30 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-06-20 8:35 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p8>
2022-06-14 1:27 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-16 22:54 ` Krzysztof Kozlowski
2022-06-14 1:34 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-05 6:21 ` Vinod Koul
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p6>
2022-06-14 1:36 ` [PATCH v3 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Wangseok Lee
2022-06-20 7:55 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-20 8:42 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p2>
2022-06-21 7:42 ` Wangseok Lee
2022-06-21 12:44 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p4>
2022-06-22 7:20 ` Wangseok Lee
2022-07-06 5:22 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-07-06 6:28 ` Krzysztof Kozlowski
2022-06-29 7:18 ` Wangseok Lee
2022-07-05 10:56 ` Krzysztof Kozlowski
2022-07-06 8:10 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-06 16:51 ` Vinod Koul
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p5>
2022-06-14 1:29 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-06-16 22:58 ` Krzysztof Kozlowski
2022-06-20 8:38 ` Wangseok Lee
2022-06-21 21:13 ` Bjorn Helgaas
[not found] ` <CGME20220621212357epcas2p41ecf1ace5d207b154cc77dac79bc7e53@epcms2p2>
2022-06-22 7:06 ` Wangseok Lee [this message]
2022-06-22 7:21 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-23 8:27 ` Krzysztof Kozlowski
2022-07-14 9:59 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-15 11:33 ` Vinod Koul
2022-06-21 7:56 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-07-06 5:20 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
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