From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: wangseok.lee@samsung.com,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"kishon@ti.com" <kishon@ti.com>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
"lars.persson@axis.com" <lars.persson@axis.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"kw@linux.com" <kw@linux.com>,
"linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>,
"kernel@axis.com" <kernel@axis.com>
Cc: Moon-Ki Jun <moonki.jun@samsung.com>,
Sang Min Kim <hypmean.kim@samsung.com>,
Dongjin Yang <dj76.yang@samsung.com>,
Yeeun Kim <yeeun119.kim@samsung.com>
Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller
Date: Thu, 23 Jun 2022 10:27:18 +0200 [thread overview]
Message-ID: <aa5c28c8-85c8-3867-69d0-2eba693594ea@linaro.org> (raw)
In-Reply-To: <20220622072159epcms2p52a21560a7e60cffd13ea70e55ac15428@epcms2p5>
On 22/06/2022 09:21, Wangseok Lee wrote:
> On 21/06/2022 21:44, Krzysztof Kozlowski wrote:
>> On 21/06/2022 09:42, Wangseok Lee wrote:
>>>>>
>>>>> samsung,syscon-bus-s-fsys:
>>>>> description:
>>>>> Phandle to bus-s path of fsys block, this register
>>>>> are used for enabling bus-s.
>>>>> $ref: /schemas/types.yaml#/definitions/phandle
>>>>>
>>>>> samsung,syscon-bus-p-fsys:
>>>>> description:
>>>>> Phandle to bus-p path of fsys block, this register
>>>>> are used for enabling bus-p.
>>>>> $ref: /schemas/types.yaml#/definitions/phandle
>>>>
>>>> This two look unspecific and hacky workaround for missing drivers. Looks
>>>> like instead of implementing interconnect or clock driver, you decided
>>>> to poke some other registers. Why this cannot be an interconnect driver?
>>>>
>>>>
>>>
>>> bus-s, bus-p is a register that exists in the sysreg of the fsys block.
>>> It is the same block as "fsys-sysreg" but is separated separately in
>>> hardware.
>>
>> Two points here:
>> 1. If it is in FSYS, why it cannot be accessed with samsung,fsys-sysreg?
>> 2. If it is only register, shuld be described like this. You must
>> describe item:
>> https://protect2.fireeye.com/v1/url?k=0f529a57-50c9a332-0f531118-000babff32e3-50938d8198077d59&q=1&e=32284e69-bbed-4d09-b6d6-0a43428aebf5&u=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv5.18-rc1%2Fsource%2FDocumentation%2Fdevicetree%2Fbindings%2Fsoc%2Fsamsung%2Fexynos-usi.yaml%23L42
>>
>
> It would be better to access with fsys-sysreg, but their h/w address are
> far from each other. The fsys block consists of a system register and an
> additional control system register. "bus-s-fsys" and "bus-p-fsys" are
> additional control system register. sysreg and additional control sysreg
> addresses are far from each other and there are h/w registers that perform
> different functions between them.
>
>>> So, get resource is performed separately from "fsys-sysreg".
>>> They set pcie slave, dbi related control settings,
>>> naming "bus-x" seems to be interconnect.
>>> I will add this description to property.
>>> I don't think it need to use the interconnect driver,
>>> so please let me know your opinion.
>>
>> Please document both in the bindings and in the driver usage of this
>> register. Writing there "0" or "1" is not enough. If the documentation
>> is good, I am fine with it. If the explanation is obfuscated/not
>> sufficient, it will look like avoiding to implement a driver, which I
>> don't want to accept.
>>
>
> I think i should add enough description. Is it sufficient to modify
> the name and description of property like this?
>
Looks ok. Thank you.
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-06-23 8:27 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7>
2022-06-14 1:16 ` [PATCH v3 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p3>
2022-06-14 1:30 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-06-20 8:35 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p8>
2022-06-14 1:27 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-16 22:54 ` Krzysztof Kozlowski
2022-06-14 1:34 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-05 6:21 ` Vinod Koul
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p6>
2022-06-14 1:36 ` [PATCH v3 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Wangseok Lee
2022-06-20 7:55 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-20 8:42 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p2>
2022-06-21 7:42 ` Wangseok Lee
2022-06-21 12:44 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p4>
2022-06-22 7:20 ` Wangseok Lee
2022-07-06 5:22 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-07-06 6:28 ` Krzysztof Kozlowski
2022-06-29 7:18 ` Wangseok Lee
2022-07-05 10:56 ` Krzysztof Kozlowski
2022-07-06 8:10 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-06 16:51 ` Vinod Koul
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p5>
2022-06-14 1:29 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-06-16 22:58 ` Krzysztof Kozlowski
2022-06-20 8:38 ` Wangseok Lee
2022-06-21 21:13 ` Bjorn Helgaas
[not found] ` <CGME20220621212357epcas2p41ecf1ace5d207b154cc77dac79bc7e53@epcms2p2>
2022-06-22 7:06 ` Wangseok Lee
2022-06-22 7:21 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-23 8:27 ` Krzysztof Kozlowski [this message]
2022-07-14 9:59 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-15 11:33 ` Vinod Koul
2022-06-21 7:56 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-07-06 5:20 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
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