From: Rob Herring <robh@kernel.org>
To: Wangseok Lee <wangseok.lee@samsung.com>
Cc: "krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"kishon@ti.com" <kishon@ti.com>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
"lars.persson@axis.com" <lars.persson@axis.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"kw@linux.com" <kw@linux.com>,
"linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>,
"kernel@axis.com" <kernel@axis.com>,
Moon-Ki Jun <moonki.jun@samsung.com>,
Sang Min Kim <hypmean.kim@samsung.com>,
Dongjin Yang <dj76.yang@samsung.com>,
Yeeun Kim <yeeun119.kim@samsung.com>
Subject: Re: [PATCH v4 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
Date: Mon, 25 Jul 2022 16:17:53 -0600 [thread overview]
Message-ID: <20220725221753.GA2838092-robh@kernel.org> (raw)
In-Reply-To: <20220720055716epcms2p60e80b1089dca0f83a894262bce676858@epcms2p6>
On Wed, Jul 20, 2022 at 02:57:16PM +0900, Wangseok Lee wrote:
> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform
> of Axis Communications and PCIe PHY is designed based on Samsung PHY.
>
> Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
> ---
> v3->v4 :
> -Add "fsys-sysreg" to properties
> -Modify the "lcpll-ref-clk" and "clocks" in properties
> "lcpll-ref-clk" is custom properties, so add 'vendor', type(enum),
> description
> Add the maxItem in clocks, add clock-names in properties
>
> v2->v3 :
> -Modify version history to fit the linux commit rule
> -Remove 'Device Tree Bindings' on title
> -Remove clock-names entries
> -Change node name to soc from artpec8 on excamples
>
> v1->v2 :
> -'make dt_binding_check' result improvement
> -Add the missing property list
> -Align the indentation of continued lines/entries
> ---
> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 85 ++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> new file mode 100644
> index 0000000..9db39ef
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARTPEC-8 SoC PCIe PHY
> +
> +maintainers:
> + - Jesper Nilsson <jesper.nilsson@axis.com>
> +
> +properties:
> + compatible:
> + const: axis,artpec8-pcie-phy
> +
> + reg:
> + items:
> + - description: PHY registers.
> + - description: PHY coding sublayer registers.
> +
> + reg-names:
> + items:
> + - const: phy
> + - const: pcs
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: ref
> +
> + samsung,fsys-sysreg:
> + description:
> + Phandle to system register of fsys block.
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> + num-lanes:
> + const: 2
Why do you need num-lanes if 2 is the only possible value?
Rob
next prev parent reply other threads:[~2022-07-25 22:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p5>
2022-07-20 5:51 ` [PATCH v4 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee
[not found] ` <CGME20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p6>
2022-07-20 5:54 ` [PATCH v4 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-07-20 14:17 ` Rob Herring
2022-07-21 8:55 ` Krzysztof Kozlowski
2022-07-20 5:57 ` [PATCH v4 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-07-21 9:13 ` Krzysztof Kozlowski
2022-07-25 22:17 ` Rob Herring [this message]
[not found] ` <CGME20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p3>
2022-07-20 6:01 ` [PATCH v4 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-07-21 9:04 ` Krzysztof Kozlowski
2022-07-21 20:58 ` Bjorn Helgaas
2022-07-22 17:36 ` Krzysztof Kozlowski
2022-07-22 19:46 ` Rob Herring
2022-07-21 20:56 ` Bjorn Helgaas
2022-07-22 20:31 ` Rob Herring
[not found] ` <CGME20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p8>
2022-07-20 6:04 ` [PATCH v4 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-20 6:18 ` [PATCH v4 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Wangseok Lee
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