* [PATCH v5 0/4] PCI EP driver support MSI doorbell from host @ 2022-08-15 21:39 Frank Li 2022-08-15 21:39 ` [PATCH v5 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Frank Li ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Frank Li @ 2022-08-15 21:39 UTC (permalink / raw) To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa ┌───────┐ ┌──────────┐ │ │ │ │ ┌─────────────┐ │ │ │ PCI Host │ │ MSI │◄┐ │ │ │ │ │ Controller │ │ │ │ │ │ └─────────────┘ └─┼───────┼──────────┼─Bar0 │ │ PCI │ │ Bar1 │ │ Func │ │ Bar2 │ │ │ │ Bar3 │ │ │ │ Bar4 │ │ ├─────────►│ │ └───────┘ └──────────┘ Many PCI controllers provided Endpoint functions. Generally PCI endpoint is hardware, which is not running a rich OS, like linux. But Linux also supports endpoint functions. PCI Host write BAR<n> space like write to memory. The EP side can't know memory changed by the Host driver. PCI Spec has not defined a standard method to do that. Only define MSI(x) to let EP notified RC status change. The basic idea is to trigger an IRQ when PCI RC writes to a memory address. That's what MSI controller provided. EP drivers just need to request a platform MSI interrupt, struct MSI_msg *msg will pass down a memory address and data. EP driver will map such memory address to one of PCI BAR<n>. Host just writes such an address to trigger EP side IRQ. If system have gic-its, only need update PCI EP side driver. But i.MX have not chip support gic-its yet. So we have to use MU to simulate a MSI controller. Although only 4 MSI IRQs are simulated, it matched vntb(pci-epf-vntb) network requirement. After enable MSI, ping delay reduce < 1ms from ~8ms IRQchip: imx mu worked as MSI controller: let imx mu worked as MSI controllers. Although IP is not design as MSI controller, we still can use it if limited IRQ number to 4. pcie: endpoint: pci-epf-vntb: add endpoint MSI support Based on ntb-next branch. https://github.com/jonmason/ntb/commits/ntb-next Using MSI as door bell registers This patch is totally independent on previous on. It can be applied to ntb-next seperately. i.MX EP function driver is upstreaming by Richard Zhu. Some dts change missed at this patches. below is reference dts change --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -160,5 +160,6 @@ pcieb_ep: pcie_ep@5f010000 { num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; + MSI-parent = <&lsio_mu12>; }; --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -172,6 +172,19 @@ lsio_mu6: mailbox@5d210000 { status = "disabled"; }; + lsio_mu12: mailbox@5d270000 { + compatible = "fsl,imx6sx-mu-MSI"; + msi-controller; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "a", "b"; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "a", "b"; + }; + Change Log - Change from v4 to v5 Fixed dt-binding document add msi-cell add interrupt max number update naming reg-names and power-domain-names. Fixed irqchip-Add-IMX-MU-MSI-controller-driver.patch rework commit message remove some field in struct imx_mu_dcfg error handle when link power domain failure. add irq_domain_update_bus_token - Change from v3 to v4 Fixed dt-binding document according to Krzysztof Kozlowski's feedback Fixed irqchip-imx-mu-worked-as-msi-controller according to Marc Zyngier's comments. There are still two important points, which I am not sure. 1. clean irq_set_affinity after platform_msi_create_irq_domain. Some function, like platform_msi_write_msg() is static. so I have to set MSI_FLAG_USE_DEF_CHIP_OPS flags, which will set irq_set_affinity to default one. 2. about comments > + msi_data->msi_domain = platform_msi_create_irq_domain( > + of_node_to_fwnode(msi_data->pdev->dev.of_node), > + &imx_mu_msi_domain_info, > + msi_data->parent); "And you don't get an error due to the fact that you use the same fwnode for both domains without overriding the domain bus token?" I did not understand yet. Fixed static check warning, reported by Dan Carpenter pcie: endpoint: pci-epf-vntb: add endpoint MSI support - Change from v2 to v3 Fixed dt-binding docment check failure Fixed typo a cover letter. Change according Bjorn's comments at patch pcie: endpoint: pci-epf-vntb: add endpoint MSI support - from V1 to V2 Fixed fsl,mu-msi.yaml's problem Fixed irq-imx-mu-msi.c problem according Marc Zyngier's feeback Added a new patch to allow pass down .pm by IRQCHIP_PLATFORM_DRIVER_END -- 2.35.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END 2022-08-15 21:39 [PATCH v5 0/4] PCI EP driver support MSI doorbell from host Frank Li @ 2022-08-15 21:39 ` Frank Li 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Frank Li @ 2022-08-15 21:39 UTC (permalink / raw) To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa IRQCHIP_PLATFORM_DRIVER_* compilation define platform_driver for irqchip. But can't set .pm field of platform_driver. Added variadic macros to set .pm field or other field if need. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- include/linux/irqchip.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h index 3a091d0710ae1..d5e6024cb2a8c 100644 --- a/include/linux/irqchip.h +++ b/include/linux/irqchip.h @@ -44,7 +44,8 @@ static const struct of_device_id drv_name##_irqchip_match_table[] = { #define IRQCHIP_MATCH(compat, fn) { .compatible = compat, \ .data = typecheck_irq_init_cb(fn), }, -#define IRQCHIP_PLATFORM_DRIVER_END(drv_name) \ + +#define IRQCHIP_PLATFORM_DRIVER_END(drv_name, ...) \ {}, \ }; \ MODULE_DEVICE_TABLE(of, drv_name##_irqchip_match_table); \ @@ -56,6 +57,7 @@ static struct platform_driver drv_name##_driver = { \ .owner = THIS_MODULE, \ .of_match_table = drv_name##_irqchip_match_table, \ .suppress_bind_attrs = true, \ + __VA_ARGS__ \ }, \ }; \ builtin_platform_driver(drv_name##_driver) -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver 2022-08-15 21:39 [PATCH v5 0/4] PCI EP driver support MSI doorbell from host Frank Li 2022-08-15 21:39 ` [PATCH v5 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Frank Li @ 2022-08-15 21:39 ` Frank Li 2022-08-16 8:39 ` kernel test robot ` (3 more replies) 2022-08-15 21:39 ` [PATCH v5 3/4] dt-bindings: irqchip: imx mu work as msi controller Frank Li 2022-08-15 21:39 ` [PATCH v5 4/4] pcie: endpoint: pci-epf-vntb: add endpoint MSI support Frank Li 3 siblings, 4 replies; 9+ messages in thread From: Frank Li @ 2022-08-15 21:39 UTC (permalink / raw) To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa The MU block found in a number of Freescale/NXP SoCs supports generating IRQs by writing data to a register This enables the MU block to be used as a MSI controller, by leveraging the platform-MSI API Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-imx-mu-msi.c | 451 +++++++++++++++++++++++++++++++ 3 files changed, 459 insertions(+) create mode 100644 drivers/irqchip/irq-imx-mu-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 5e4e50122777d..4599471d880c0 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -470,6 +470,13 @@ config IMX_INTMUX help Support for the i.MX INTMUX interrupt multiplexer. +config IMX_MU_MSI + bool "i.MX MU work as MSI controller" + default y if ARCH_MXC + select IRQ_DOMAIN + help + MU work as MSI controller to do general doorbell + config LS1X_IRQ bool "Loongson-1 Interrupt Controller" depends on MACH_LOONGSON32 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 5d8e21d3dc6d8..870423746c783 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o +obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c new file mode 100644 index 0000000000000..1930c47c3570d --- /dev/null +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Freescale MU worked as MSI controller + * + * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> + * Copyright 2022 NXP + * Frank Li <Frank.Li@nxp.com> + * Peng Fan <peng.fan@nxp.com> + * + * Based on drivers/mailbox/imx-mailbox.c + */ +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/msi.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/irqchip.h> +#include <linux/irqdomain.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/spinlock.h> +#include <linux/dma-iommu.h> +#include <linux/pm_runtime.h> +#include <linux/pm_domain.h> + + +#define IMX_MU_CHANS 4 + +enum imx_mu_xcr { + IMX_MU_GIER, + IMX_MU_GCR, + IMX_MU_TCR, + IMX_MU_RCR, + IMX_MU_xCR_MAX, +}; + +enum imx_mu_xsr { + IMX_MU_SR, + IMX_MU_GSR, + IMX_MU_TSR, + IMX_MU_RSR, +}; + +enum imx_mu_type { + IMX_MU_V1 = BIT(0), + IMX_MU_V2 = BIT(1), + IMX_MU_V2_S4 = BIT(15), +}; + +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +#define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) + +struct imx_mu_dcfg { + enum imx_mu_type type; + u32 xTR; /* Transmit Register0 */ + u32 xRR; /* Receive Register0 */ + u32 xSR[4]; /* Status Registers */ + u32 xCR[4]; /* Control Registers */ +}; + +struct imx_mu_msi { + spinlock_t lock; + raw_spinlock_t reglock; + struct irq_domain *msi_domain; + void __iomem *regs; + phys_addr_t msiir_addr; + const struct imx_mu_dcfg *cfg; + unsigned long used; + struct clk *clk; +}; + +static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs) +{ + iowrite32(val, msi_data->regs + offs); +} + +static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs) +{ + return ioread32(msi_data->regs + offs); +} + +static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr) +{ + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&msi_data->reglock, flags); + val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); + val &= ~clr; + val |= set; + imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); + raw_spin_unlock_irqrestore(&msi_data->reglock, flags); + + return val; +} + +static void imx_mu_msi_parent_mask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq)); +} + +static void imx_mu_msi_parent_unmask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0); +} + +static void imx_mu_msi_parent_ack_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4); +} + +static struct irq_chip imx_mu_msi_irq_chip = { + .name = "MU-MSI", + .irq_ack = irq_chip_ack_parent, +}; + +static struct msi_domain_ops imx_mu_msi_irq_ops = { +}; + +static struct msi_domain_info imx_mu_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops = &imx_mu_msi_irq_ops, + .chip = &imx_mu_msi_irq_chip, +}; + +static void imx_mu_msi_parent_compose_msg(struct irq_data *data, + struct msi_msg *msg) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + u64 addr = msi_data->msiir_addr + 4 * data->hwirq; + + msg->address_hi = upper_32_bits(addr); + msg->address_lo = lower_32_bits(addr); + msg->data = data->hwirq; +} + +static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip imx_mu_msi_parent_chip = { + .name = "MU", + .irq_mask = imx_mu_msi_parent_mask_irq, + .irq_unmask = imx_mu_msi_parent_unmask_irq, + .irq_ack = imx_mu_msi_parent_ack_irq, + .irq_compose_msi_msg = imx_mu_msi_parent_compose_msg, + .irq_set_affinity = imx_mu_msi_parent_set_affinity, +}; + +static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct imx_mu_msi *msi_data = domain->host_data; + unsigned long flags; + int pos, err = 0; + + WARN_ON(nr_irqs != 1); + + spin_lock_irqsave(&msi_data->lock, flags); + pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); + if (pos < IMX_MU_CHANS) + __set_bit(pos, &msi_data->used); + else + err = -ENOSPC; + spin_unlock_irqrestore(&msi_data->lock, flags); + + if (err) + return err; + + irq_domain_set_info(domain, virq, pos, + &imx_mu_msi_parent_chip, msi_data, + handle_edge_irq, NULL, NULL); + return 0; +} + +static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); + unsigned long flags; + + spin_lock_irqsave(&msi_data->lock, flags); + __clear_bit(d->hwirq, &msi_data->used); + spin_unlock_irqrestore(&msi_data->lock, flags); +} + +static const struct irq_domain_ops imx_mu_msi_domain_ops = { + .alloc = imx_mu_msi_domain_irq_alloc, + .free = imx_mu_msi_domain_irq_free, +}; + +static void imx_mu_msi_irq_handler(struct irq_desc *desc) +{ + struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 status; + int i; + + status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); + + chained_irq_enter(chip, desc); + for (i = 0; i < IMX_MU_CHANS; i++) { + if (status & IMX_MU_xSR_RFn(msi_data, i)) + generic_handle_domain_irq(msi_data->msi_domain, i); + } + chained_irq_exit(chip, desc); +} + +static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) +{ + struct fwnode_handle *fwnodes = dev_fwnode(dev); + struct irq_domain *parent; + + /* Initialize MSI domain parent */ + parent = irq_domain_create_linear(fwnodes, + IMX_MU_CHANS, + &imx_mu_msi_domain_ops, + msi_data); + if (!parent) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); + + msi_data->msi_domain = platform_msi_create_irq_domain( + fwnodes, + &imx_mu_msi_domain_info, + parent); + + if (!msi_data->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(parent); + return -ENOMEM; + } + + irq_domain_set_pm_device(msi_data->msi_domain, dev); + + return 0; +} + +/* Register offset of different version MU IP */ +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { + .xTR = 0x0, + .xRR = 0x10, + .xSR = {0x20, 0x20, 0x20, 0x20}, + .xCR = {0x24, 0x24, 0x24, 0x24}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { + .xTR = 0x20, + .xRR = 0x40, + .xSR = {0x60, 0x60, 0x60, 0x60}, + .xCR = {0x64, 0x64, 0x64, 0x64}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { + .type = IMX_MU_V2, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { + + .type = IMX_MU_V2 | IMX_MU_V2_S4, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + +static int __init imx_mu_of_init(struct device_node *dn, + struct device_node *parent, + const struct imx_mu_dcfg *cfg + ) +{ + struct platform_device *pdev = of_find_device_by_node(dn); + struct imx_mu_msi *msi_data, *priv; + struct device_link *pd_link_a; + struct device_link *pd_link_b; + struct resource *res; + struct device *pd_a; + struct device *pd_b; + struct device *dev; + int ret; + int irq; + + if (!pdev) + return -ENODEV; + + dev = &pdev->dev; + + priv = msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); + if (!msi_data) + return -ENOMEM; + + msi_data->cfg = cfg; + + msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor a-facing"); + if (IS_ERR(msi_data->regs)) { + dev_err(&pdev->dev, "failed to initialize 'regs'\n"); + return PTR_ERR(msi_data->regs); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor b-facing"); + if (!res) + return -EIO; + + msi_data->msiir_addr = res->start + msi_data->cfg->xTR; + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return -ENODEV; + + platform_set_drvdata(pdev, msi_data); + + msi_data->clk = devm_clk_get(dev, NULL); + if (IS_ERR(msi_data->clk)) { + if (PTR_ERR(msi_data->clk) != -ENOENT) + return PTR_ERR(msi_data->clk); + + msi_data->clk = NULL; + } + + pd_a = dev_pm_domain_attach_by_name(dev, "processor a-facing"); + if (IS_ERR(pd_a)) + return PTR_ERR(pd_a); + + pd_b = dev_pm_domain_attach_by_name(dev, "processor b-facing"); + if (IS_ERR(pd_b)) + return PTR_ERR(pd_b); + + pd_link_a = device_link_add(dev, pd_a, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + if (!pd_link_a) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + goto err_pd_a; + } + + pd_link_b = device_link_add(dev, pd_b, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + + if (!pd_link_b) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + goto err_pd_b; + } + + ret = imx_mu_msi_domains_init(msi_data, dev); + if (ret) + goto err_dm_init; + + irq_set_chained_handler_and_data(irq, + imx_mu_msi_irq_handler, + msi_data); + + pm_runtime_enable(dev); + + return 0; + +err_dm_init: + device_link_remove(dev, pd_b); +err_pd_b: + device_link_remove(dev, pd_a); +err_pd_a: + return -EINVAL; +} + +static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) +{ + struct imx_mu_msi *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int __maybe_unused imx_mu_runtime_resume(struct device *dev) +{ + struct imx_mu_msi *priv = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) + dev_err(dev, "failed to enable clock\n"); + + return ret; +} + +static const struct dev_pm_ops imx_mu_pm_ops = { + SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, + imx_mu_runtime_resume, NULL) +}; + +static int __init imx_mu_imx7ulp_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp); +} + +static int __init imx_mu_imx6sx_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx); +} + +static int __init imx_mu_imx8ulp_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp); +} + +static int __init imx_mu_imx8ulp_s4_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp_s4); +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi) +IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init) +IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init) +IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init) +IRQCHIP_MATCH("fsl,imx8ulp-mu-msi-s4", imx_mu_imx8ulp_s4_of_init) +IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops) + + +MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>"); +MODULE_DESCRIPTION("Freescale MU MSI controller driver"); +MODULE_LICENSE("GPL"); -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li @ 2022-08-16 8:39 ` kernel test robot 2022-08-16 19:04 ` kernel test robot ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2022-08-16 8:39 UTC (permalink / raw) To: Frank Li, maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: llvm, kbuild-all, linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa Hi Frank, I love your patch! Perhaps something to improve: [auto build test WARNING on jonmason-ntb/ntb-next] [also build test WARNING on robh/for-next linus/master v6.0-rc1 next-20220816] [cannot apply to tip/irq/core] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 base: https://github.com/jonmason/ntb ntb-next config: arm64-randconfig-r025-20220815 (https://download.01.org/0day-ci/archive/20220816/202208161638.7Rn1SHT2-lkp@intel.com/config) compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project aed5e3bea138ce581d682158eb61c27b3cfdd6ec) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # https://github.com/intel-lab-lkp/linux/commit/71296e2ad757d90e870b2ab81f2b06b9c76e7c41 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 git checkout 71296e2ad757d90e870b2ab81f2b06b9c76e7c41 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/irqchip/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> drivers/irqchip/irq-imx-mu-msi.c:295:32: warning: variable 'priv' set but not used [-Wunused-but-set-variable] struct imx_mu_msi *msi_data, *priv; ^ 1 warning generated. vim +/priv +295 drivers/irqchip/irq-imx-mu-msi.c 288 289 static int __init imx_mu_of_init(struct device_node *dn, 290 struct device_node *parent, 291 const struct imx_mu_dcfg *cfg 292 ) 293 { 294 struct platform_device *pdev = of_find_device_by_node(dn); > 295 struct imx_mu_msi *msi_data, *priv; 296 struct device_link *pd_link_a; 297 struct device_link *pd_link_b; 298 struct resource *res; 299 struct device *pd_a; 300 struct device *pd_b; 301 struct device *dev; 302 int ret; 303 int irq; 304 305 if (!pdev) 306 return -ENODEV; 307 308 dev = &pdev->dev; 309 310 priv = msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); 311 if (!msi_data) 312 return -ENOMEM; 313 314 msi_data->cfg = cfg; 315 316 msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor a-facing"); 317 if (IS_ERR(msi_data->regs)) { 318 dev_err(&pdev->dev, "failed to initialize 'regs'\n"); 319 return PTR_ERR(msi_data->regs); 320 } 321 322 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor b-facing"); 323 if (!res) 324 return -EIO; 325 326 msi_data->msiir_addr = res->start + msi_data->cfg->xTR; 327 328 irq = platform_get_irq(pdev, 0); 329 if (irq <= 0) 330 return -ENODEV; 331 332 platform_set_drvdata(pdev, msi_data); 333 334 msi_data->clk = devm_clk_get(dev, NULL); 335 if (IS_ERR(msi_data->clk)) { 336 if (PTR_ERR(msi_data->clk) != -ENOENT) 337 return PTR_ERR(msi_data->clk); 338 339 msi_data->clk = NULL; 340 } 341 342 pd_a = dev_pm_domain_attach_by_name(dev, "processor a-facing"); 343 if (IS_ERR(pd_a)) 344 return PTR_ERR(pd_a); 345 346 pd_b = dev_pm_domain_attach_by_name(dev, "processor b-facing"); 347 if (IS_ERR(pd_b)) 348 return PTR_ERR(pd_b); 349 350 pd_link_a = device_link_add(dev, pd_a, 351 DL_FLAG_STATELESS | 352 DL_FLAG_PM_RUNTIME | 353 DL_FLAG_RPM_ACTIVE); 354 355 if (!pd_link_a) { 356 dev_err(dev, "Failed to add device_link to mu a.\n"); 357 goto err_pd_a; 358 } 359 360 pd_link_b = device_link_add(dev, pd_b, 361 DL_FLAG_STATELESS | 362 DL_FLAG_PM_RUNTIME | 363 DL_FLAG_RPM_ACTIVE); 364 365 366 if (!pd_link_b) { 367 dev_err(dev, "Failed to add device_link to mu a.\n"); 368 goto err_pd_b; 369 } 370 371 ret = imx_mu_msi_domains_init(msi_data, dev); 372 if (ret) 373 goto err_dm_init; 374 375 irq_set_chained_handler_and_data(irq, 376 imx_mu_msi_irq_handler, 377 msi_data); 378 379 pm_runtime_enable(dev); 380 381 return 0; 382 383 err_dm_init: 384 device_link_remove(dev, pd_b); 385 err_pd_b: 386 device_link_remove(dev, pd_a); 387 err_pd_a: 388 return -EINVAL; 389 } 390 -- 0-DAY CI Kernel Test Service https://01.org/lkp ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li 2022-08-16 8:39 ` kernel test robot @ 2022-08-16 19:04 ` kernel test robot 2022-08-16 22:07 ` kernel test robot 2022-08-16 23:19 ` kernel test robot 3 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2022-08-16 19:04 UTC (permalink / raw) To: Frank Li, maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: llvm, kbuild-all, linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa Hi Frank, I love your patch! Yet something to improve: [auto build test ERROR on jonmason-ntb/ntb-next] [also build test ERROR on robh/for-next linus/master v6.0-rc1 next-20220816] [cannot apply to tip/irq/core] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 base: https://github.com/jonmason/ntb ntb-next config: arm-multi_v5_defconfig (https://download.01.org/0day-ci/archive/20220817/202208170210.zGxvHnIZ-lkp@intel.com/config) compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project aed5e3bea138ce581d682158eb61c27b3cfdd6ec) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/intel-lab-lkp/linux/commit/71296e2ad757d90e870b2ab81f2b06b9c76e7c41 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 git checkout 71296e2ad757d90e870b2ab81f2b06b9c76e7c41 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> drivers/irqchip/irq-imx-mu-msi.c:124:13: error: use of undeclared identifier 'irq_chip_ack_parent' .irq_ack = irq_chip_ack_parent, ^ drivers/irqchip/irq-imx-mu-msi.c:127:30: error: variable has incomplete type 'struct msi_domain_ops' static struct msi_domain_ops imx_mu_msi_irq_ops = { ^ drivers/irqchip/irq-imx-mu-msi.c:127:15: note: forward declaration of 'struct msi_domain_ops' static struct msi_domain_ops imx_mu_msi_irq_ops = { ^ drivers/irqchip/irq-imx-mu-msi.c:131:12: error: use of undeclared identifier 'MSI_FLAG_USE_DEF_DOM_OPS' .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), ^ drivers/irqchip/irq-imx-mu-msi.c:131:39: error: use of undeclared identifier 'MSI_FLAG_USE_DEF_CHIP_OPS' .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), ^ drivers/irqchip/irq-imx-mu-msi.c:130:31: error: variable has incomplete type 'struct msi_domain_info' static struct msi_domain_info imx_mu_msi_domain_info = { ^ drivers/irqchip/irq-imx-mu-msi.c:130:15: note: forward declaration of 'struct msi_domain_info' static struct msi_domain_info imx_mu_msi_domain_info = { ^ drivers/irqchip/irq-imx-mu-msi.c:203:3: error: field designator 'alloc' does not refer to any field in type 'const struct irq_domain_ops' .alloc = imx_mu_msi_domain_irq_alloc, ^ drivers/irqchip/irq-imx-mu-msi.c:204:3: error: field designator 'free' does not refer to any field in type 'const struct irq_domain_ops' .free = imx_mu_msi_domain_irq_free, ^ drivers/irqchip/irq-imx-mu-msi.c:241:25: error: call to undeclared function 'platform_msi_create_irq_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] msi_data->msi_domain = platform_msi_create_irq_domain( ^ drivers/irqchip/irq-imx-mu-msi.c:295:32: warning: variable 'priv' set but not used [-Wunused-but-set-variable] struct imx_mu_msi *msi_data, *priv; ^ 1 warning and 8 errors generated. vim +/irq_chip_ack_parent +124 drivers/irqchip/irq-imx-mu-msi.c 121 122 static struct irq_chip imx_mu_msi_irq_chip = { 123 .name = "MU-MSI", > 124 .irq_ack = irq_chip_ack_parent, 125 }; 126 -- 0-DAY CI Kernel Test Service https://01.org/lkp ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li 2022-08-16 8:39 ` kernel test robot 2022-08-16 19:04 ` kernel test robot @ 2022-08-16 22:07 ` kernel test robot 2022-08-16 23:19 ` kernel test robot 3 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2022-08-16 22:07 UTC (permalink / raw) To: Frank Li, maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: kbuild-all, linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa Hi Frank, I love your patch! Yet something to improve: [auto build test ERROR on jonmason-ntb/ntb-next] [also build test ERROR on robh/for-next linus/master v6.0-rc1 next-20220816] [cannot apply to tip/irq/core] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 base: https://github.com/jonmason/ntb ntb-next config: arm-vf610m4_defconfig (https://download.01.org/0day-ci/archive/20220817/202208170522.PGyjHgNg-lkp@intel.com/config) compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/71296e2ad757d90e870b2ab81f2b06b9c76e7c41 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 git checkout 71296e2ad757d90e870b2ab81f2b06b9c76e7c41 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/irqchip/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com> All error/warnings (new ones prefixed by >>): >> drivers/irqchip/irq-imx-mu-msi.c:127:15: error: variable 'imx_mu_msi_irq_ops' has initializer but incomplete type 127 | static struct msi_domain_ops imx_mu_msi_irq_ops = { | ^~~~~~~~~~~~~~ drivers/irqchip/irq-imx-mu-msi.c:130:15: error: variable 'imx_mu_msi_domain_info' has initializer but incomplete type 130 | static struct msi_domain_info imx_mu_msi_domain_info = { | ^~~~~~~~~~~~~~~ drivers/irqchip/irq-imx-mu-msi.c:131:10: error: 'struct msi_domain_info' has no member named 'flags' 131 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), | ^~~~~ drivers/irqchip/irq-imx-mu-msi.c:131:20: error: 'MSI_FLAG_USE_DEF_DOM_OPS' undeclared here (not in a function) 131 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-imx-mu-msi.c:131:47: error: 'MSI_FLAG_USE_DEF_CHIP_OPS' undeclared here (not in a function) 131 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-imx-mu-msi.c:131:19: warning: excess elements in struct initializer 131 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), | ^ drivers/irqchip/irq-imx-mu-msi.c:131:19: note: (near initialization for 'imx_mu_msi_domain_info') drivers/irqchip/irq-imx-mu-msi.c:132:10: error: 'struct msi_domain_info' has no member named 'ops' 132 | .ops = &imx_mu_msi_irq_ops, | ^~~ drivers/irqchip/irq-imx-mu-msi.c:132:19: warning: excess elements in struct initializer 132 | .ops = &imx_mu_msi_irq_ops, | ^ drivers/irqchip/irq-imx-mu-msi.c:132:19: note: (near initialization for 'imx_mu_msi_domain_info') drivers/irqchip/irq-imx-mu-msi.c:133:10: error: 'struct msi_domain_info' has no member named 'chip' 133 | .chip = &imx_mu_msi_irq_chip, | ^~~~ drivers/irqchip/irq-imx-mu-msi.c:133:19: warning: excess elements in struct initializer 133 | .chip = &imx_mu_msi_irq_chip, | ^ drivers/irqchip/irq-imx-mu-msi.c:133:19: note: (near initialization for 'imx_mu_msi_domain_info') drivers/irqchip/irq-imx-mu-msi.c: In function 'imx_mu_msi_domains_init': drivers/irqchip/irq-imx-mu-msi.c:241:32: error: implicit declaration of function 'platform_msi_create_irq_domain' [-Werror=implicit-function-declaration] 241 | msi_data->msi_domain = platform_msi_create_irq_domain( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-imx-mu-msi.c:241:30: warning: assignment to 'struct irq_domain *' from 'int' makes pointer from integer without a cast [-Wint-conversion] 241 | msi_data->msi_domain = platform_msi_create_irq_domain( | ^ drivers/irqchip/irq-imx-mu-msi.c: In function 'imx_mu_of_init': >> drivers/irqchip/irq-imx-mu-msi.c:295:39: warning: variable 'priv' set but not used [-Wunused-but-set-variable] 295 | struct imx_mu_msi *msi_data, *priv; | ^~~~ drivers/irqchip/irq-imx-mu-msi.c: At top level: >> drivers/irqchip/irq-imx-mu-msi.c:127:30: error: storage size of 'imx_mu_msi_irq_ops' isn't known 127 | static struct msi_domain_ops imx_mu_msi_irq_ops = { | ^~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-imx-mu-msi.c:130:31: error: storage size of 'imx_mu_msi_domain_info' isn't known 130 | static struct msi_domain_info imx_mu_msi_domain_info = { | ^~~~~~~~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +/imx_mu_msi_irq_ops +127 drivers/irqchip/irq-imx-mu-msi.c 126 > 127 static struct msi_domain_ops imx_mu_msi_irq_ops = { 128 }; 129 130 static struct msi_domain_info imx_mu_msi_domain_info = { 131 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 132 .ops = &imx_mu_msi_irq_ops, 133 .chip = &imx_mu_msi_irq_chip, 134 }; 135 136 static void imx_mu_msi_parent_compose_msg(struct irq_data *data, 137 struct msi_msg *msg) 138 { 139 struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 140 u64 addr = msi_data->msiir_addr + 4 * data->hwirq; 141 142 msg->address_hi = upper_32_bits(addr); 143 msg->address_lo = lower_32_bits(addr); 144 msg->data = data->hwirq; 145 } 146 147 static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, 148 const struct cpumask *mask, bool force) 149 { 150 return -EINVAL; 151 } 152 153 static struct irq_chip imx_mu_msi_parent_chip = { 154 .name = "MU", 155 .irq_mask = imx_mu_msi_parent_mask_irq, 156 .irq_unmask = imx_mu_msi_parent_unmask_irq, 157 .irq_ack = imx_mu_msi_parent_ack_irq, 158 .irq_compose_msi_msg = imx_mu_msi_parent_compose_msg, 159 .irq_set_affinity = imx_mu_msi_parent_set_affinity, 160 }; 161 162 static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, 163 unsigned int virq, 164 unsigned int nr_irqs, 165 void *args) 166 { 167 struct imx_mu_msi *msi_data = domain->host_data; 168 unsigned long flags; 169 int pos, err = 0; 170 171 WARN_ON(nr_irqs != 1); 172 173 spin_lock_irqsave(&msi_data->lock, flags); 174 pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); 175 if (pos < IMX_MU_CHANS) 176 __set_bit(pos, &msi_data->used); 177 else 178 err = -ENOSPC; 179 spin_unlock_irqrestore(&msi_data->lock, flags); 180 181 if (err) 182 return err; 183 184 irq_domain_set_info(domain, virq, pos, 185 &imx_mu_msi_parent_chip, msi_data, 186 handle_edge_irq, NULL, NULL); 187 return 0; 188 } 189 190 static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, 191 unsigned int virq, unsigned int nr_irqs) 192 { 193 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 194 struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); 195 unsigned long flags; 196 197 spin_lock_irqsave(&msi_data->lock, flags); 198 __clear_bit(d->hwirq, &msi_data->used); 199 spin_unlock_irqrestore(&msi_data->lock, flags); 200 } 201 202 static const struct irq_domain_ops imx_mu_msi_domain_ops = { 203 .alloc = imx_mu_msi_domain_irq_alloc, 204 .free = imx_mu_msi_domain_irq_free, 205 }; 206 207 static void imx_mu_msi_irq_handler(struct irq_desc *desc) 208 { 209 struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); 210 struct irq_chip *chip = irq_desc_get_chip(desc); 211 u32 status; 212 int i; 213 214 status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); 215 216 chained_irq_enter(chip, desc); 217 for (i = 0; i < IMX_MU_CHANS; i++) { 218 if (status & IMX_MU_xSR_RFn(msi_data, i)) 219 generic_handle_domain_irq(msi_data->msi_domain, i); 220 } 221 chained_irq_exit(chip, desc); 222 } 223 224 static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) 225 { 226 struct fwnode_handle *fwnodes = dev_fwnode(dev); 227 struct irq_domain *parent; 228 229 /* Initialize MSI domain parent */ 230 parent = irq_domain_create_linear(fwnodes, 231 IMX_MU_CHANS, 232 &imx_mu_msi_domain_ops, 233 msi_data); 234 if (!parent) { 235 dev_err(dev, "failed to create IRQ domain\n"); 236 return -ENOMEM; 237 } 238 239 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 240 241 msi_data->msi_domain = platform_msi_create_irq_domain( 242 fwnodes, 243 &imx_mu_msi_domain_info, 244 parent); 245 246 if (!msi_data->msi_domain) { 247 dev_err(dev, "failed to create MSI domain\n"); 248 irq_domain_remove(parent); 249 return -ENOMEM; 250 } 251 252 irq_domain_set_pm_device(msi_data->msi_domain, dev); 253 254 return 0; 255 } 256 257 /* Register offset of different version MU IP */ 258 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 259 .xTR = 0x0, 260 .xRR = 0x10, 261 .xSR = {0x20, 0x20, 0x20, 0x20}, 262 .xCR = {0x24, 0x24, 0x24, 0x24}, 263 }; 264 265 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 266 .xTR = 0x20, 267 .xRR = 0x40, 268 .xSR = {0x60, 0x60, 0x60, 0x60}, 269 .xCR = {0x64, 0x64, 0x64, 0x64}, 270 }; 271 272 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 273 .type = IMX_MU_V2, 274 .xTR = 0x200, 275 .xRR = 0x280, 276 .xSR = {0xC, 0x118, 0x124, 0x12C}, 277 .xCR = {0x110, 0x114, 0x120, 0x128}, 278 }; 279 280 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { 281 282 .type = IMX_MU_V2 | IMX_MU_V2_S4, 283 .xTR = 0x200, 284 .xRR = 0x280, 285 .xSR = {0xC, 0x118, 0x124, 0x12C}, 286 .xCR = {0x110, 0x114, 0x120, 0x128}, 287 }; 288 289 static int __init imx_mu_of_init(struct device_node *dn, 290 struct device_node *parent, 291 const struct imx_mu_dcfg *cfg 292 ) 293 { 294 struct platform_device *pdev = of_find_device_by_node(dn); > 295 struct imx_mu_msi *msi_data, *priv; 296 struct device_link *pd_link_a; 297 struct device_link *pd_link_b; 298 struct resource *res; 299 struct device *pd_a; 300 struct device *pd_b; 301 struct device *dev; 302 int ret; 303 int irq; 304 305 if (!pdev) 306 return -ENODEV; 307 308 dev = &pdev->dev; 309 310 priv = msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); 311 if (!msi_data) 312 return -ENOMEM; 313 314 msi_data->cfg = cfg; 315 316 msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor a-facing"); 317 if (IS_ERR(msi_data->regs)) { 318 dev_err(&pdev->dev, "failed to initialize 'regs'\n"); 319 return PTR_ERR(msi_data->regs); 320 } 321 322 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor b-facing"); 323 if (!res) 324 return -EIO; 325 326 msi_data->msiir_addr = res->start + msi_data->cfg->xTR; 327 328 irq = platform_get_irq(pdev, 0); 329 if (irq <= 0) 330 return -ENODEV; 331 332 platform_set_drvdata(pdev, msi_data); 333 334 msi_data->clk = devm_clk_get(dev, NULL); 335 if (IS_ERR(msi_data->clk)) { 336 if (PTR_ERR(msi_data->clk) != -ENOENT) 337 return PTR_ERR(msi_data->clk); 338 339 msi_data->clk = NULL; 340 } 341 342 pd_a = dev_pm_domain_attach_by_name(dev, "processor a-facing"); 343 if (IS_ERR(pd_a)) 344 return PTR_ERR(pd_a); 345 346 pd_b = dev_pm_domain_attach_by_name(dev, "processor b-facing"); 347 if (IS_ERR(pd_b)) 348 return PTR_ERR(pd_b); 349 350 pd_link_a = device_link_add(dev, pd_a, 351 DL_FLAG_STATELESS | 352 DL_FLAG_PM_RUNTIME | 353 DL_FLAG_RPM_ACTIVE); 354 355 if (!pd_link_a) { 356 dev_err(dev, "Failed to add device_link to mu a.\n"); 357 goto err_pd_a; 358 } 359 360 pd_link_b = device_link_add(dev, pd_b, 361 DL_FLAG_STATELESS | 362 DL_FLAG_PM_RUNTIME | 363 DL_FLAG_RPM_ACTIVE); 364 365 366 if (!pd_link_b) { 367 dev_err(dev, "Failed to add device_link to mu a.\n"); 368 goto err_pd_b; 369 } 370 371 ret = imx_mu_msi_domains_init(msi_data, dev); 372 if (ret) 373 goto err_dm_init; 374 375 irq_set_chained_handler_and_data(irq, 376 imx_mu_msi_irq_handler, 377 msi_data); 378 379 pm_runtime_enable(dev); 380 381 return 0; 382 383 err_dm_init: 384 device_link_remove(dev, pd_b); 385 err_pd_b: 386 device_link_remove(dev, pd_a); 387 err_pd_a: 388 return -EINVAL; 389 } 390 -- 0-DAY CI Kernel Test Service https://01.org/lkp ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li ` (2 preceding siblings ...) 2022-08-16 22:07 ` kernel test robot @ 2022-08-16 23:19 ` kernel test robot 3 siblings, 0 replies; 9+ messages in thread From: kernel test robot @ 2022-08-16 23:19 UTC (permalink / raw) To: Frank Li, maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: llvm, kbuild-all, linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa Hi Frank, I love your patch! Yet something to improve: [auto build test ERROR on jonmason-ntb/ntb-next] [also build test ERROR on robh/for-next linus/master v6.0-rc1 next-20220816] [cannot apply to tip/irq/core] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 base: https://github.com/jonmason/ntb ntb-next config: arm-imx_v4_v5_defconfig (https://download.01.org/0day-ci/archive/20220817/202208170756.pO5LueSf-lkp@intel.com/config) compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project aed5e3bea138ce581d682158eb61c27b3cfdd6ec) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/intel-lab-lkp/linux/commit/71296e2ad757d90e870b2ab81f2b06b9c76e7c41 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Frank-Li/PCI-EP-driver-support-MSI-doorbell-from-host/20220816-131930 git checkout 71296e2ad757d90e870b2ab81f2b06b9c76e7c41 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> drivers/irqchip/irq-imx-mu-msi.c:124:13: error: use of undeclared identifier 'irq_chip_ack_parent' .irq_ack = irq_chip_ack_parent, ^ >> drivers/irqchip/irq-imx-mu-msi.c:127:30: error: variable has incomplete type 'struct msi_domain_ops' static struct msi_domain_ops imx_mu_msi_irq_ops = { ^ drivers/irqchip/irq-imx-mu-msi.c:127:15: note: forward declaration of 'struct msi_domain_ops' static struct msi_domain_ops imx_mu_msi_irq_ops = { ^ >> drivers/irqchip/irq-imx-mu-msi.c:131:12: error: use of undeclared identifier 'MSI_FLAG_USE_DEF_DOM_OPS' .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), ^ >> drivers/irqchip/irq-imx-mu-msi.c:131:39: error: use of undeclared identifier 'MSI_FLAG_USE_DEF_CHIP_OPS' .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), ^ >> drivers/irqchip/irq-imx-mu-msi.c:130:31: error: variable has incomplete type 'struct msi_domain_info' static struct msi_domain_info imx_mu_msi_domain_info = { ^ drivers/irqchip/irq-imx-mu-msi.c:130:15: note: forward declaration of 'struct msi_domain_info' static struct msi_domain_info imx_mu_msi_domain_info = { ^ >> drivers/irqchip/irq-imx-mu-msi.c:203:3: error: field designator 'alloc' does not refer to any field in type 'const struct irq_domain_ops' .alloc = imx_mu_msi_domain_irq_alloc, ^ >> drivers/irqchip/irq-imx-mu-msi.c:204:3: error: field designator 'free' does not refer to any field in type 'const struct irq_domain_ops' .free = imx_mu_msi_domain_irq_free, ^ >> drivers/irqchip/irq-imx-mu-msi.c:241:25: error: call to undeclared function 'platform_msi_create_irq_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] msi_data->msi_domain = platform_msi_create_irq_domain( ^ drivers/irqchip/irq-imx-mu-msi.c:295:32: warning: variable 'priv' set but not used [-Wunused-but-set-variable] struct imx_mu_msi *msi_data, *priv; ^ 1 warning and 8 errors generated. vim +/irq_chip_ack_parent +124 drivers/irqchip/irq-imx-mu-msi.c 121 122 static struct irq_chip imx_mu_msi_irq_chip = { 123 .name = "MU-MSI", > 124 .irq_ack = irq_chip_ack_parent, 125 }; 126 > 127 static struct msi_domain_ops imx_mu_msi_irq_ops = { 128 }; 129 > 130 static struct msi_domain_info imx_mu_msi_domain_info = { > 131 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 132 .ops = &imx_mu_msi_irq_ops, 133 .chip = &imx_mu_msi_irq_chip, 134 }; 135 136 static void imx_mu_msi_parent_compose_msg(struct irq_data *data, 137 struct msi_msg *msg) 138 { 139 struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 140 u64 addr = msi_data->msiir_addr + 4 * data->hwirq; 141 142 msg->address_hi = upper_32_bits(addr); 143 msg->address_lo = lower_32_bits(addr); 144 msg->data = data->hwirq; 145 } 146 147 static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, 148 const struct cpumask *mask, bool force) 149 { 150 return -EINVAL; 151 } 152 153 static struct irq_chip imx_mu_msi_parent_chip = { 154 .name = "MU", 155 .irq_mask = imx_mu_msi_parent_mask_irq, 156 .irq_unmask = imx_mu_msi_parent_unmask_irq, 157 .irq_ack = imx_mu_msi_parent_ack_irq, 158 .irq_compose_msi_msg = imx_mu_msi_parent_compose_msg, 159 .irq_set_affinity = imx_mu_msi_parent_set_affinity, 160 }; 161 162 static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, 163 unsigned int virq, 164 unsigned int nr_irqs, 165 void *args) 166 { 167 struct imx_mu_msi *msi_data = domain->host_data; 168 unsigned long flags; 169 int pos, err = 0; 170 171 WARN_ON(nr_irqs != 1); 172 173 spin_lock_irqsave(&msi_data->lock, flags); 174 pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); 175 if (pos < IMX_MU_CHANS) 176 __set_bit(pos, &msi_data->used); 177 else 178 err = -ENOSPC; 179 spin_unlock_irqrestore(&msi_data->lock, flags); 180 181 if (err) 182 return err; 183 184 irq_domain_set_info(domain, virq, pos, 185 &imx_mu_msi_parent_chip, msi_data, 186 handle_edge_irq, NULL, NULL); 187 return 0; 188 } 189 190 static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, 191 unsigned int virq, unsigned int nr_irqs) 192 { 193 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 194 struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); 195 unsigned long flags; 196 197 spin_lock_irqsave(&msi_data->lock, flags); 198 __clear_bit(d->hwirq, &msi_data->used); 199 spin_unlock_irqrestore(&msi_data->lock, flags); 200 } 201 202 static const struct irq_domain_ops imx_mu_msi_domain_ops = { > 203 .alloc = imx_mu_msi_domain_irq_alloc, > 204 .free = imx_mu_msi_domain_irq_free, 205 }; 206 207 static void imx_mu_msi_irq_handler(struct irq_desc *desc) 208 { 209 struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); 210 struct irq_chip *chip = irq_desc_get_chip(desc); 211 u32 status; 212 int i; 213 214 status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); 215 216 chained_irq_enter(chip, desc); 217 for (i = 0; i < IMX_MU_CHANS; i++) { 218 if (status & IMX_MU_xSR_RFn(msi_data, i)) 219 generic_handle_domain_irq(msi_data->msi_domain, i); 220 } 221 chained_irq_exit(chip, desc); 222 } 223 224 static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) 225 { 226 struct fwnode_handle *fwnodes = dev_fwnode(dev); 227 struct irq_domain *parent; 228 229 /* Initialize MSI domain parent */ 230 parent = irq_domain_create_linear(fwnodes, 231 IMX_MU_CHANS, 232 &imx_mu_msi_domain_ops, 233 msi_data); 234 if (!parent) { 235 dev_err(dev, "failed to create IRQ domain\n"); 236 return -ENOMEM; 237 } 238 239 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 240 > 241 msi_data->msi_domain = platform_msi_create_irq_domain( 242 fwnodes, 243 &imx_mu_msi_domain_info, 244 parent); 245 246 if (!msi_data->msi_domain) { 247 dev_err(dev, "failed to create MSI domain\n"); 248 irq_domain_remove(parent); 249 return -ENOMEM; 250 } 251 252 irq_domain_set_pm_device(msi_data->msi_domain, dev); 253 254 return 0; 255 } 256 -- 0-DAY CI Kernel Test Service https://01.org/lkp ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 3/4] dt-bindings: irqchip: imx mu work as msi controller 2022-08-15 21:39 [PATCH v5 0/4] PCI EP driver support MSI doorbell from host Frank Li 2022-08-15 21:39 ` [PATCH v5 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Frank Li 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li @ 2022-08-15 21:39 ` Frank Li 2022-08-15 21:39 ` [PATCH v5 4/4] pcie: endpoint: pci-epf-vntb: add endpoint MSI support Frank Li 3 siblings, 0 replies; 9+ messages in thread From: Frank Li @ 2022-08-15 21:39 UTC (permalink / raw) To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa I.MX mu support generate irq by write a register. Provide msi controller support so other driver such as PCI EP can use it by standard msi interface as doorbell. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../interrupt-controller/fsl,mu-msi.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml new file mode 100644 index 0000000000000..ac07b138e24c0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor (A side) to signal the other processor (B side) using + interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-facing, Processor B-facing). + + MU can work as msi interrupt controller to do doorbell + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx6sx-mu-msi + - fsl,imx7ulp-mu-msi + - fsl,imx8ulp-mu-msi + - fsl,imx8ulp-mu-msi-s4 + + reg: + items: + - description: a side register base address + - description: b side register base address + + reg-names: + items: + - const: processor a-facing + - const: processor b-facing + + interrupts: + description: a side interrupt number. + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + items: + - description: a side power domain + - description: b side power domain + + power-domain-names: + items: + - const: processor a-facing + - const: processor b-facing + + interrupt-controller: true + + msi-controller: true + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - msi-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + msi-controller@5d270000 { + compatible = "fsl,imx6sx-mu-msi"; + msi-controller; + #msi-cells = <0>; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "processor a-facing", "processor b-facing"; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "processor a-facing", "processor b-facing"; + }; -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 4/4] pcie: endpoint: pci-epf-vntb: add endpoint MSI support 2022-08-15 21:39 [PATCH v5 0/4] PCI EP driver support MSI doorbell from host Frank Li ` (2 preceding siblings ...) 2022-08-15 21:39 ` [PATCH v5 3/4] dt-bindings: irqchip: imx mu work as msi controller Frank Li @ 2022-08-15 21:39 ` Frank Li 3 siblings, 0 replies; 9+ messages in thread From: Frank Li @ 2022-08-15 21:39 UTC (permalink / raw) To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw, bhelgaas Cc: linux-kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon, lorenzo.pieralisi, ntb, lznuaa ┌───────┐ ┌──────────┐ │ │ │ │ ┌─────────────┐ │ │ │ PCI Host │ │ MSI │◄┐ │ │ │ │ │ Controller │ │ │ │ │ │ └─────────────┘ └─┼───────┼──────────┼─BAR0 │ │ PCI │ │ BAR1 │ │ Func │ │ BAR2 │ │ │ │ BAR3 │ │ │ │ BAR4 │ │ ├─────────►│ │ └───────┘ └──────────┘ Linux supports endpoint functions. PCI Host write BAR<n> space like write to memory. The EP side can't know memory changed by the host driver. PCI Spec has not defined a standard method to do that. Only define MSI(x) to let EP notified RC status change. The basic idea is to trigger an IRQ when PCI RC writes to a memory address. That's what MSI controller provided. EP drivers just need to request a platform MSI interrupt, struct msi_msg *msg will pass down a memory address and data. EP driver will map such memory address to one of PCI BAR<n>. Host just writes such an address to trigger EP side irq. Add MSI support for pci-epf-vntb. pci-epf-vntb driver query if system have MSI controller. Setup doorbell address according to struct msi_msg. So PCIe host can write this doorbell address to triger EP side's irq. If no MSI controller exist, fall back to software polling. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 134 +++++++++++++++--- 1 file changed, 112 insertions(+), 22 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index 1466dd1904175..ad4f7ec8a39fc 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -44,6 +44,7 @@ #include <linux/pci-epc.h> #include <linux/pci-epf.h> #include <linux/ntb.h> +#include <linux/msi.h> static struct workqueue_struct *kpcintb_workqueue; @@ -143,6 +144,8 @@ struct epf_ntb { void __iomem *vpci_mw_addr[MAX_MW]; struct delayed_work cmd_handler; + + int msi_virqbase; }; #define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group) @@ -253,7 +256,7 @@ static void epf_ntb_cmd_handler(struct work_struct *work) ntb = container_of(work, struct epf_ntb, cmd_handler.work); - for (i = 1; i < ntb->db_count; i++) { + for (i = 1; i < ntb->db_count && !ntb->epf_db_phy; i++) { if (readl(ntb->epf_db + i * 4)) { if (readl(ntb->epf_db + i * 4)) ntb->db |= 1 << (i - 1); @@ -454,11 +457,9 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) ctrl->num_mws = ntb->num_mws; ntb->spad_size = spad_size; - ctrl->db_entry_size = 4; - for (i = 0; i < ntb->db_count; i++) { ntb->reg->db_data[i] = 1 + i; - ntb->reg->db_offset[i] = 0; + ntb->reg->db_offset[i] = 4 * i; } return 0; @@ -509,6 +510,28 @@ static int epf_ntb_configure_interrupt(struct epf_ntb *ntb) return 0; } +static int epf_ntb_db_size(struct epf_ntb *ntb) +{ + const struct pci_epc_features *epc_features; + size_t size = 4 * ntb->db_count; + u32 align; + + epc_features = pci_epc_get_features(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no); + align = epc_features->align; + + if (size < 128) + size = 128; + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); + + return size; +} + /** * epf_ntb_db_bar_init() - Configure Doorbell window BARs * @ntb: NTB device that facilitates communication between HOST and vHOST @@ -520,35 +543,33 @@ static int epf_ntb_db_bar_init(struct epf_ntb *ntb) struct device *dev = &ntb->epf->dev; int ret; struct pci_epf_bar *epf_bar; - void __iomem *mw_addr; + void __iomem *mw_addr = NULL; enum pci_barno barno; - size_t size = 4 * ntb->db_count; + size_t size; epc_features = pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no); align = epc_features->align; - - if (size < 128) - size = 128; - - if (align) - size = ALIGN(size, align); - else - size = roundup_pow_of_two(size); + size = epf_ntb_db_size(ntb); barno = ntb->epf_ntb_bar[BAR_DB]; + epf_bar = &ntb->epf->bar[barno]; - mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); - if (!mw_addr) { - dev_err(dev, "Failed to allocate OB address\n"); - return -ENOMEM; + if (!ntb->epf_db_phy) { + mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); + if (!mw_addr) { + dev_err(dev, "Failed to allocate OB address\n"); + return -ENOMEM; + } + } else { + epf_bar->phys_addr = ntb->epf_db_phy; + epf_bar->barno = barno; + epf_bar->size = size; } ntb->epf_db = mw_addr; - epf_bar = &ntb->epf->bar[barno]; - ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar); if (ret) { dev_err(dev, "Doorbell BAR set failed\n"); @@ -704,6 +725,74 @@ static int epf_ntb_init_epc_bar(struct epf_ntb *ntb) return 0; } +static void epf_ntb_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct epf_ntb *ntb = dev_get_drvdata(desc->dev); + struct epf_ntb_ctrl *reg = ntb->reg; + int size = epf_ntb_db_size(ntb); + u64 addr; + + addr = msg->address_hi; + addr <<= 32; + addr |= msg->address_lo; + + reg->db_data[desc->msi_index] = msg->data; + + if (desc->msi_index == 0) + ntb->epf_db_phy = round_down(addr, size); + + reg->db_offset[desc->msi_index] = addr - ntb->epf_db_phy; +} + +static irqreturn_t epf_ntb_interrupt_handler(int irq, void *data) +{ + struct epf_ntb *ntb = data; + int index; + + index = irq - ntb->msi_virqbase; + ntb->db |= 1 << (index - 1); + ntb_db_event(&ntb->ntb, index); + + return IRQ_HANDLED; +} + +static void epf_ntb_epc_msi_init(struct epf_ntb *ntb) +{ + struct device *dev = &ntb->epf->dev; + struct irq_domain *domain; + int virq; + int ret; + int i; + + domain = dev_get_msi_domain(ntb->epf->epc->dev.parent); + if (!domain) + return; + + dev_set_msi_domain(dev, domain); + + if (platform_msi_domain_alloc_irqs(&ntb->epf->dev, + ntb->db_count, + epf_ntb_write_msi_msg)) { + dev_info(dev, "Can't allocate MSI, fall back to poll mode\n"); + return; + } + + dev_info(dev, "vntb use MSI as doorbell\n"); + + for (i = 0; i < ntb->db_count; i++) { + virq = msi_get_virq(dev, i); + ret = devm_request_irq(dev, virq, + epf_ntb_interrupt_handler, 0, + "ntb", ntb); + + if (ret) + dev_err(dev, "devm_request_irq() failure\n"); + + if (!i) + ntb->msi_virqbase = virq; + } +} + /** * epf_ntb_epc_init() - Initialize NTB interface * @ntb: NTB device that facilitates communication between HOST and vHOST2 @@ -1299,14 +1388,15 @@ static int epf_ntb_bind(struct pci_epf *epf) goto err_bar_alloc; } + epf_set_drvdata(epf, ntb); + epf_ntb_epc_msi_init(ntb); + ret = epf_ntb_epc_init(ntb); if (ret) { dev_err(dev, "Failed to initialize EPC\n"); goto err_bar_alloc; } - epf_set_drvdata(epf, ntb); - pci_space[0] = (ntb->vntb_pid << 16) | ntb->vntb_vid; pci_vntb_table[0].vendor = ntb->vntb_vid; pci_vntb_table[0].device = ntb->vntb_pid; -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-08-16 23:20 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-08-15 21:39 [PATCH v5 0/4] PCI EP driver support MSI doorbell from host Frank Li 2022-08-15 21:39 ` [PATCH v5 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Frank Li 2022-08-15 21:39 ` [PATCH v5 2/4] irqchip: Add IMX MU MSI controller driver Frank Li 2022-08-16 8:39 ` kernel test robot 2022-08-16 19:04 ` kernel test robot 2022-08-16 22:07 ` kernel test robot 2022-08-16 23:19 ` kernel test robot 2022-08-15 21:39 ` [PATCH v5 3/4] dt-bindings: irqchip: imx mu work as msi controller Frank Li 2022-08-15 21:39 ` [PATCH v5 4/4] pcie: endpoint: pci-epf-vntb: add endpoint MSI support Frank Li
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