* [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
@ 2022-08-16 10:20 Mika Westerberg
2022-08-22 3:18 ` Sathyanarayanan Kuppuswamy
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Mika Westerberg @ 2022-08-16 10:20 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Russell Currey, oohall, Paul Menzel, Lukas Wunner,
Mika Westerberg, linux-pci
There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
accidentally clears the root port PIO log size even though it should be 4.
Fix the affected root ports by forcing the log size to be 4 if it is set
to 0. The BIOS for the next generation CPUs should have this fixed.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/pci/pcie/dpc.c | 13 ++++++++-----
drivers/pci/quirks.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
index 3e9afee02e8d..ab06c801a2c1 100644
--- a/drivers/pci/pcie/dpc.c
+++ b/drivers/pci/pcie/dpc.c
@@ -335,11 +335,14 @@ void pci_dpc_init(struct pci_dev *pdev)
return;
pdev->dpc_rp_extensions = true;
- pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
- if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
- pci_err(pdev, "RP PIO log size %u is invalid\n",
- pdev->dpc_rp_log_size);
- pdev->dpc_rp_log_size = 0;
+ /* If not already set by the quirk in quirks.c */
+ if (!pdev->dpc_rp_log_size) {
+ pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
+ if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
+ pci_err(pdev, "RP PIO log size %u is invalid\n",
+ pdev->dpc_rp_log_size);
+ pdev->dpc_rp_log_size = 0;
+ }
}
}
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 4944798e75b5..260d8b50f68d 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5956,3 +5956,40 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
#endif
+
+#ifdef CONFIG_PCIE_DPC
+/*
+ * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
+ * log size of the integrated Thunderbolt PCIe root ports so we quirk
+ * them here.
+ */
+static void dpc_log_size(struct pci_dev *dev)
+{
+ u16 dpc_cap, val;
+
+ dpc_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
+ if (!dpc_cap)
+ return;
+
+ pci_read_config_word(dev, dpc_cap + PCI_EXP_DPC_CAP, &val);
+ if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
+ return;
+
+ if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
+ pci_info(dev, "quirking RP PIO log size\n");
+ dev->dpc_rp_log_size = 4;
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
+#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
@ 2022-08-22 3:18 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:19 ` Sathyanarayanan Kuppuswamy
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sathyanarayanan Kuppuswamy @ 2022-08-22 3:18 UTC (permalink / raw)
To: Mika Westerberg, Bjorn Helgaas
Cc: Russell Currey, oohall, Paul Menzel, Lukas Wunner, linux-pci
On 8/16/22 3:20 AM, Mika Westerberg wrote:
> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Looks good to me.
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> ---
> drivers/pci/pcie/dpc.c | 13 ++++++++-----
> drivers/pci/quirks.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
> index 3e9afee02e8d..ab06c801a2c1 100644
> --- a/drivers/pci/pcie/dpc.c
> +++ b/drivers/pci/pcie/dpc.c
> @@ -335,11 +335,14 @@ void pci_dpc_init(struct pci_dev *pdev)
> return;
>
> pdev->dpc_rp_extensions = true;
> - pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> - if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> - pci_err(pdev, "RP PIO log size %u is invalid\n",
> - pdev->dpc_rp_log_size);
> - pdev->dpc_rp_log_size = 0;
> + /* If not already set by the quirk in quirks.c */
> + if (!pdev->dpc_rp_log_size) {
> + pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> + if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> + pci_err(pdev, "RP PIO log size %u is invalid\n",
> + pdev->dpc_rp_log_size);
> + pdev->dpc_rp_log_size = 0;
> + }
> }
> }
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 4944798e75b5..260d8b50f68d 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5956,3 +5956,40 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
> #endif
> +
> +#ifdef CONFIG_PCIE_DPC
> +/*
> + * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
> + * log size of the integrated Thunderbolt PCIe root ports so we quirk
> + * them here.
> + */
> +static void dpc_log_size(struct pci_dev *dev)
> +{
> + u16 dpc_cap, val;
> +
> + dpc_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
> + if (!dpc_cap)
> + return;
> +
> + pci_read_config_word(dev, dpc_cap + PCI_EXP_DPC_CAP, &val);
> + if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
> + return;
> +
> + if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
> + pci_info(dev, "quirking RP PIO log size\n");
> + dev->dpc_rp_log_size = 4;
> + }
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
> +#endif
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
2022-08-22 3:18 ` Sathyanarayanan Kuppuswamy
@ 2022-08-22 3:19 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:43 ` Krzysztof Wilczyński
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sathyanarayanan Kuppuswamy @ 2022-08-22 3:19 UTC (permalink / raw)
To: Mika Westerberg, Bjorn Helgaas
Cc: Russell Currey, oohall, Paul Menzel, Lukas Wunner, linux-pci
Hi,
On 8/16/22 3:20 AM, Mika Westerberg wrote:
> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Looks good to me.
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> ---
> drivers/pci/pcie/dpc.c | 13 ++++++++-----
> drivers/pci/quirks.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
> index 3e9afee02e8d..ab06c801a2c1 100644
> --- a/drivers/pci/pcie/dpc.c
> +++ b/drivers/pci/pcie/dpc.c
> @@ -335,11 +335,14 @@ void pci_dpc_init(struct pci_dev *pdev)
> return;
>
> pdev->dpc_rp_extensions = true;
> - pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> - if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> - pci_err(pdev, "RP PIO log size %u is invalid\n",
> - pdev->dpc_rp_log_size);
> - pdev->dpc_rp_log_size = 0;
> + /* If not already set by the quirk in quirks.c */
> + if (!pdev->dpc_rp_log_size) {
> + pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> + if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> + pci_err(pdev, "RP PIO log size %u is invalid\n",
> + pdev->dpc_rp_log_size);
> + pdev->dpc_rp_log_size = 0;
> + }
> }
> }
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 4944798e75b5..260d8b50f68d 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5956,3 +5956,40 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
> #endif
> +
> +#ifdef CONFIG_PCIE_DPC
> +/*
> + * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
> + * log size of the integrated Thunderbolt PCIe root ports so we quirk
> + * them here.
> + */
> +static void dpc_log_size(struct pci_dev *dev)
> +{
> + u16 dpc_cap, val;
> +
> + dpc_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
> + if (!dpc_cap)
> + return;
> +
> + pci_read_config_word(dev, dpc_cap + PCI_EXP_DPC_CAP, &val);
> + if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
> + return;
> +
> + if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
> + pci_info(dev, "quirking RP PIO log size\n");
> + dev->dpc_rp_log_size = 4;
> + }
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
> +#endif
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
2022-08-22 3:18 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:19 ` Sathyanarayanan Kuppuswamy
@ 2022-08-22 3:43 ` Krzysztof Wilczyński
2022-09-27 22:40 ` Bjorn Helgaas
2022-09-27 23:13 ` Bjorn Helgaas
4 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Wilczyński @ 2022-08-22 3:43 UTC (permalink / raw)
To: Mika Westerberg
Cc: Bjorn Helgaas, Russell Currey, oohall, Paul Menzel, Lukas Wunner,
linux-pci, Sasha Levin
[Adding Sasha for visibility]
Hi Mika,
> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.
Thank you for the fix!
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
I've added Sasha, as there is probably a lot of the 11th and 12th
generation of Intel hardware out there that might warrant a backport
to stable kernels.
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
` (2 preceding siblings ...)
2022-08-22 3:43 ` Krzysztof Wilczyński
@ 2022-09-27 22:40 ` Bjorn Helgaas
2022-09-27 23:13 ` Bjorn Helgaas
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2022-09-27 22:40 UTC (permalink / raw)
To: Mika Westerberg
Cc: Bjorn Helgaas, Russell Currey, oohall, Paul Menzel, Lukas Wunner,
linux-pci
On Tue, Aug 16, 2022 at 01:20:42PM +0300, Mika Westerberg wrote:
> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---
> drivers/pci/pcie/dpc.c | 13 ++++++++-----
> drivers/pci/quirks.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
> index 3e9afee02e8d..ab06c801a2c1 100644
> --- a/drivers/pci/pcie/dpc.c
> +++ b/drivers/pci/pcie/dpc.c
> @@ -335,11 +335,14 @@ void pci_dpc_init(struct pci_dev *pdev)
> return;
>
> pdev->dpc_rp_extensions = true;
> - pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> - if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> - pci_err(pdev, "RP PIO log size %u is invalid\n",
> - pdev->dpc_rp_log_size);
> - pdev->dpc_rp_log_size = 0;
> + /* If not already set by the quirk in quirks.c */
> + if (!pdev->dpc_rp_log_size) {
> + pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> + if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> + pci_err(pdev, "RP PIO log size %u is invalid\n",
> + pdev->dpc_rp_log_size);
> + pdev->dpc_rp_log_size = 0;
> + }
> }
> }
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 4944798e75b5..260d8b50f68d 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5956,3 +5956,40 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
> #endif
> +
> +#ifdef CONFIG_PCIE_DPC
> +/*
> + * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
> + * log size of the integrated Thunderbolt PCIe root ports so we quirk
> + * them here.
> + */
> +static void dpc_log_size(struct pci_dev *dev)
> +{
> + u16 dpc_cap, val;
> +
> + dpc_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
> + if (!dpc_cap)
> + return;
> +
> + pci_read_config_word(dev, dpc_cap + PCI_EXP_DPC_CAP, &val);
> + if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
> + return;
> +
> + if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
> + pci_info(dev, "quirking RP PIO log size\n");
> + dev->dpc_rp_log_size = 4;
Just to clarify here, I originally thought this was only a cosmetic
fix, and the "DPC: RP PIO log size 0 is invalid" could be ignored.
I guess it's true that it can be ignored, but it *also* means that
dpc_process_rp_pio_error() will not dump the RP PIO Header Log even
though these devices support the RP Extensions and implement the RP
PIO Log registers, right?
> + }
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
> +#endif
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
` (3 preceding siblings ...)
2022-09-27 22:40 ` Bjorn Helgaas
@ 2022-09-27 23:13 ` Bjorn Helgaas
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2022-09-27 23:13 UTC (permalink / raw)
To: Mika Westerberg
Cc: Bjorn Helgaas, Russell Currey, oohall, Paul Menzel, Lukas Wunner,
linux-pci
On Tue, Aug 16, 2022 at 01:20:42PM +0300, Mika Westerberg wrote:
> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Applied to pci/dpc for v6.1, thanks, Mika!
I updated the commit log to include the fact that the bug also
prevents dumping the RP PIO Log registers, so let me know if that's
not accurate:
PCI/DPC: Quirk PIO log size for certain Intel Root Ports
Some Root Ports on Intel Tiger Lake and Alder Lake systems support the RP
Extensions for DPC and the RP PIO Log registers but incorrectly advertise
an RP PIO Log Size of zero. This means the kernel complains that:
DPC: RP PIO log size 0 is invalid
and if DPC is triggered, the DPC driver will not dump the RP PIO Log
registers when it should.
This is caused by a BIOS bug and should be fixed the BIOS for future CPUs.
Add a quirk to set the correct RP PIO Log size for the affected Root Ports.
> ---
> drivers/pci/pcie/dpc.c | 13 ++++++++-----
> drivers/pci/quirks.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
> index 3e9afee02e8d..ab06c801a2c1 100644
> --- a/drivers/pci/pcie/dpc.c
> +++ b/drivers/pci/pcie/dpc.c
> @@ -335,11 +335,14 @@ void pci_dpc_init(struct pci_dev *pdev)
> return;
>
> pdev->dpc_rp_extensions = true;
> - pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> - if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> - pci_err(pdev, "RP PIO log size %u is invalid\n",
> - pdev->dpc_rp_log_size);
> - pdev->dpc_rp_log_size = 0;
> + /* If not already set by the quirk in quirks.c */
> + if (!pdev->dpc_rp_log_size) {
> + pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
> + if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
> + pci_err(pdev, "RP PIO log size %u is invalid\n",
> + pdev->dpc_rp_log_size);
> + pdev->dpc_rp_log_size = 0;
> + }
> }
> }
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 4944798e75b5..260d8b50f68d 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5956,3 +5956,40 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
> #endif
> +
> +#ifdef CONFIG_PCIE_DPC
> +/*
> + * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
> + * log size of the integrated Thunderbolt PCIe root ports so we quirk
> + * them here.
> + */
> +static void dpc_log_size(struct pci_dev *dev)
> +{
> + u16 dpc_cap, val;
> +
> + dpc_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
> + if (!dpc_cap)
> + return;
> +
> + pci_read_config_word(dev, dpc_cap + PCI_EXP_DPC_CAP, &val);
> + if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
> + return;
> +
> + if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
> + pci_info(dev, "quirking RP PIO log size\n");
> + dev->dpc_rp_log_size = 4;
> + }
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
> +#endif
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-27 23:14 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
2022-08-22 3:18 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:19 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:43 ` Krzysztof Wilczyński
2022-09-27 22:40 ` Bjorn Helgaas
2022-09-27 23:13 ` Bjorn Helgaas
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).