From: Vidya Sagar <vidyas@nvidia.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>,
<mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>,
<ffclaire1224@gmail.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V2 4/9] PCI: tegra194: Handle errors in BPMP response
Date: Mon, 26 Sep 2022 17:20:33 +0530 [thread overview]
Message-ID: <20220926115038.24727-5-vidyas@nvidia.com> (raw)
In-Reply-To: <20220926115038.24727-1-vidyas@nvidia.com>
The return value from tegra_bpmp_transfer indicates the success or
failure of the IPC transaction with BPMP. If the transaction
succeeded, we also need to check the actual command's result code.
Add code to do this.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 7d6e54a12eff..0268eacdae48 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1203,6 +1203,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
struct mrq_uphy_response resp;
struct tegra_bpmp_message msg;
struct mrq_uphy_request req;
+ int err;
/*
* Controller-5 doesn't need to have its state set by BPMP-FW in
@@ -1225,7 +1226,13 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
msg.rx.data = &resp;
msg.rx.size = sizeof(resp);
- return tegra_bpmp_transfer(pcie->bpmp, &msg);
+ err = tegra_bpmp_transfer(pcie->bpmp, &msg);
+ if (err)
+ return err;
+ if (msg.rx.ret)
+ return -EINVAL;
+
+ return 0;
}
static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
@@ -1234,6 +1241,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
struct mrq_uphy_response resp;
struct tegra_bpmp_message msg;
struct mrq_uphy_request req;
+ int err;
memset(&req, 0, sizeof(req));
memset(&resp, 0, sizeof(resp));
@@ -1253,7 +1261,13 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
msg.rx.data = &resp;
msg.rx.size = sizeof(resp);
- return tegra_bpmp_transfer(pcie->bpmp, &msg);
+ err = tegra_bpmp_transfer(pcie->bpmp, &msg);
+ if (err)
+ return err;
+ if (msg.rx.ret)
+ return -EINVAL;
+
+ return 0;
}
static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
--
2.17.1
next prev parent reply other threads:[~2022-09-26 13:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 11:50 [PATCH V2 0/9] Enhancements to pcie-tegra194 driver Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 1/9] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 2/9] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 3/9] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar
2022-09-26 11:50 ` Vidya Sagar [this message]
2022-09-26 11:50 ` [PATCH V2 5/9] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 6/9] PCI: tegra194: Refactor LTSSM state polling on surprise down Vidya Sagar
2022-09-26 18:16 ` Bjorn Helgaas
2022-09-26 11:50 ` [PATCH V2 7/9] PCI: tegra194: Disable direct speed change for EP Vidya Sagar
2022-09-26 11:50 ` [PATCH V2 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar
2022-09-26 18:18 ` Bjorn Helgaas
2022-09-26 11:50 ` [PATCH V2 9/9] PCI: tegra194: Calibrate P2U for endpoint mode Vidya Sagar
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