[PATCH V2 0/2] Disable PTM for endpoint mode

[PATCH V2 0/2] Disable PTM for endpoint mode

[Vidya Sagar]

This patch series contains patches to disable PTM for endpoint mode
as the PCIe compliance tool requires the PTM be disabled for the endpoint
mode.

V2:
* Addressed review comments from Jingoo Han

Vidya Sagar (2):
  PCI: Add PCI_PTM_CAP_RES macro
  PCI: designware-ep: Disable PTM capabilities for EP mode

 .../pci/controller/dwc/pcie-designware-ep.c    | 18 ++++++++++++++++++
 include/uapi/linux/pci_regs.h                  |  1 +
 2 files changed, 19 insertions(+)

-- 
2.17.1

[PATCH V2 1/2] PCI: Add PCI_PTM_CAP_RES macro

[Vidya Sagar]

Add macro defining Responder capable bit in Precision Time Measurement
capability register.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
---
V2:
* Added "Reviewed-by: Jingoo Han <jingoohan1@gmail.com>"

 include/uapi/linux/pci_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 57b8e2ffb1dd..1c3591c8e09e 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1058,6 +1058,7 @@
 /* Precision Time Measurement */
 #define PCI_PTM_CAP			0x04	    /* PTM Capability */
 #define  PCI_PTM_CAP_REQ		0x00000001  /* Requester capable */
+#define  PCI_PTM_CAP_RES		0x00000002  /* Responder capable */
 #define  PCI_PTM_CAP_ROOT		0x00000004  /* Root capable */
 #define  PCI_PTM_GRANULARITY_MASK	0x0000FF00  /* Clock granularity */
 #define PCI_PTM_CTRL			0x08	    /* PTM Control */
-- 
2.17.1

[PATCH V2 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode

[Vidya Sagar]

Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
in the EP mode. The PCIe compliance for the EP mode expects PTM
capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
Hence disable PTM for the EP mode.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
---
V2:
* Addressed review comment from Jingoo Han
* Added "Reviewed-by: Jingoo Han <jingoohan1@gmail.com>"

 .../pci/controller/dwc/pcie-designware-ep.c    | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 095fb0291ec9..b88b6597194a 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -638,6 +638,7 @@ static int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 	struct dw_pcie_ep_func *ep_func;
 	struct device *dev = pci->dev;
 	struct pci_epc *epc = ep->epc;
+	unsigned int ptm_cap_base;
 	unsigned int offset;
 	unsigned int nbars;
 	u8 hdr_type;
@@ -690,6 +691,7 @@ static int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 	}
 
 	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+	ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
 
 	dw_pcie_dbi_ro_wr_en(pci);
 
@@ -702,6 +704,22 @@ static int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
 	}
 
+	/*
+	 * PTM responder capability can be disabled only after disabling
+	 * PTM root capability.
+	 */
+	if (ptm_cap_base) {
+		dw_pcie_dbi_ro_wr_en(pci);
+		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
+		reg &= ~PCI_PTM_CAP_ROOT;
+		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
+
+		reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
+		reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
+		dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
+		dw_pcie_dbi_ro_wr_dis(pci);
+	}
+
 	dw_pcie_setup(pci);
 	dw_pcie_dbi_ro_wr_dis(pci);
 
-- 
2.17.1

Re: [PATCH V2 1/2] PCI: Add PCI_PTM_CAP_RES macro

[Bjorn Helgaas]

On Mon, Sep 26, 2022 at 04:40:16PM +0530, Vidya Sagar wrote:
> Add macro defining Responder capable bit in Precision Time Measurement
> capability register.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
> V2:
> * Added "Reviewed-by: Jingoo Han <jingoohan1@gmail.com>"
> 
>  include/uapi/linux/pci_regs.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..1c3591c8e09e 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1058,6 +1058,7 @@
>  /* Precision Time Measurement */
>  #define PCI_PTM_CAP			0x04	    /* PTM Capability */
>  #define  PCI_PTM_CAP_REQ		0x00000001  /* Requester capable */
> +#define  PCI_PTM_CAP_RES		0x00000002  /* Responder capable */
>  #define  PCI_PTM_CAP_ROOT		0x00000004  /* Root capable */
>  #define  PCI_PTM_GRANULARITY_MASK	0x0000FF00  /* Clock granularity */
>  #define PCI_PTM_CTRL			0x08	    /* PTM Control */
> -- 
> 2.17.1
> 

Re: [PATCH V2 0/2] Disable PTM for endpoint mode

[Vidya Sagar]

Hi Lorenzo,
Do you have any further comments on this series?

Thanks,
Vidya Sagar

On 9/26/2022 4:40 PM, Vidya Sagar wrote:
> This patch series contains patches to disable PTM for endpoint mode
> as the PCIe compliance tool requires the PTM be disabled for the endpoint
> mode.
> 
> V2:
> * Addressed review comments from Jingoo Han
> 
> Vidya Sagar (2):
>    PCI: Add PCI_PTM_CAP_RES macro
>    PCI: designware-ep: Disable PTM capabilities for EP mode
> 
>   .../pci/controller/dwc/pcie-designware-ep.c    | 18 ++++++++++++++++++
>   include/uapi/linux/pci_regs.h                  |  1 +
>   2 files changed, 19 insertions(+)
>