[PATCH v5 0/4] PCI: add 4x lane support for pci-j721e controllers

[PATCH v5 0/4] PCI: add 4x lane support for pci-j721e controllers

[Matt Ranostay]

Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.

Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
  regressions on 1-2x lane platforms

Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a unsigned
  integer
* Update CC list

Changes from v3:
* Use the max_lanes setting per chip for the mask size required since bootloader
  could have set num_lanes to a higher value that the device tree which would leave
  in an undefined state
* Reorder patches do the previous change to not break bisect
* Remove line breaking for dev_warn to allow better grepping and since no strict
  80 columns anymore

Changes from v4:
* Correct invalid settings for j7200 PCIe RC + EP
* Add j784s4 configuration for selection of 4x lanes

Matt Ranostay (4):
  PCI: j721e: Add per platform maximum lane settings
  PCI: j721e: Add PCIe 4x lane selection support
  PCI: j721e: add j784s4 PCIe configuration
  PCI: j721e: Add warnings on num-lanes misconfiguration

 drivers/pci/controller/cadence/pci-j721e.c | 51 +++++++++++++++++++---
 1 file changed, 46 insertions(+), 5 deletions(-)

-- 
2.38.GIT

[PATCH v5 1/4] PCI: j721e: Add per platform maximum lane settings

[Matt Ranostay]

Various platforms have different maximum amount of lanes that
can be selected. Add max_lanes to struct j721e_pcie to allow
for error checking on num-lanes selection from device tree.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..875224d34958 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -48,8 +48,6 @@ enum link_status {
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
 
-#define MAX_LANES			2
-
 struct j721e_pcie {
 	struct cdns_pcie	*cdns_pcie;
 	struct clk		*refclk;
@@ -72,6 +70,7 @@ struct j721e_pcie_data {
 	unsigned int		quirk_disable_flr:1;
 	u32			linkdown_irq_regfield;
 	unsigned int		byte_access_allowed:1;
+	unsigned int		max_lanes;
 };
 
 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
 	.quirk_retrain_flag = true,
 	.byte_access_allowed = false,
 	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 2,
 };
 
 static const struct j721e_pcie_data j721e_pcie_ep_data = {
 	.mode = PCI_MODE_EP,
 	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 2,
 };
 
 static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
 	.quirk_detect_quiet_flag = true,
 	.linkdown_irq_regfield = J7200_LINK_DOWN,
 	.byte_access_allowed = true,
+	.max_lanes = 2,
 };
 
 static const struct j721e_pcie_data j7200_pcie_ep_data = {
 	.mode = PCI_MODE_EP,
 	.quirk_detect_quiet_flag = true,
 	.quirk_disable_flr = true,
+	.max_lanes = 2,
 };
 
 static const struct j721e_pcie_data am64_pcie_rc_data = {
 	.mode = PCI_MODE_RC,
 	.linkdown_irq_regfield = J7200_LINK_DOWN,
 	.byte_access_allowed = true,
+	.max_lanes = 1,
 };
 
 static const struct j721e_pcie_data am64_pcie_ep_data = {
 	.mode = PCI_MODE_EP,
 	.linkdown_irq_regfield = J7200_LINK_DOWN,
+	.max_lanes = 1,
 };
 
 static const struct of_device_id of_j721e_pcie_match[] = {
@@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 	pcie->user_cfg_base = base;
 
 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
-	if (ret || num_lanes > MAX_LANES)
+	if (ret || num_lanes > data->max_lanes)
 		num_lanes = 1;
 	pcie->num_lanes = num_lanes;
 
-- 
2.38.GIT

Re: [PATCH v5 1/4] PCI: j721e: Add per platform maximum lane settings

[Lorenzo Pieralisi]

On Wed, Nov 09, 2022 at 12:25:53AM -0800, Matt Ranostay wrote:
> Various platforms have different maximum amount of lanes that
> can be selected. Add max_lanes to struct j721e_pcie to allow
> for error checking on num-lanes selection from device tree.

https://lore.kernel.org/linux-pci/CAL_JsqJ5cOLXhD-73esmhVwMEWGT+w3SJC14Z0jY4tQJQRA7iw@mail.gmail.com

Why have you reposted this patch ?

Lorenzo

> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>  drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..875224d34958 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -48,8 +48,6 @@ enum link_status {
>  
>  #define GENERATION_SEL_MASK		GENMASK(1, 0)
>  
> -#define MAX_LANES			2
> -
>  struct j721e_pcie {
>  	struct cdns_pcie	*cdns_pcie;
>  	struct clk		*refclk;
> @@ -72,6 +70,7 @@ struct j721e_pcie_data {
>  	unsigned int		quirk_disable_flr:1;
>  	u32			linkdown_irq_regfield;
>  	unsigned int		byte_access_allowed:1;
> +	unsigned int		max_lanes;
>  };
>  
>  static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
> @@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
>  	.quirk_retrain_flag = true,
>  	.byte_access_allowed = false,
>  	.linkdown_irq_regfield = LINK_DOWN,
> +	.max_lanes = 2,
>  };
>  
>  static const struct j721e_pcie_data j721e_pcie_ep_data = {
>  	.mode = PCI_MODE_EP,
>  	.linkdown_irq_regfield = LINK_DOWN,
> +	.max_lanes = 2,
>  };
>  
>  static const struct j721e_pcie_data j7200_pcie_rc_data = {
> @@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
>  	.quirk_detect_quiet_flag = true,
>  	.linkdown_irq_regfield = J7200_LINK_DOWN,
>  	.byte_access_allowed = true,
> +	.max_lanes = 2,
>  };
>  
>  static const struct j721e_pcie_data j7200_pcie_ep_data = {
>  	.mode = PCI_MODE_EP,
>  	.quirk_detect_quiet_flag = true,
>  	.quirk_disable_flr = true,
> +	.max_lanes = 2,
>  };
>  
>  static const struct j721e_pcie_data am64_pcie_rc_data = {
>  	.mode = PCI_MODE_RC,
>  	.linkdown_irq_regfield = J7200_LINK_DOWN,
>  	.byte_access_allowed = true,
> +	.max_lanes = 1,
>  };
>  
>  static const struct j721e_pcie_data am64_pcie_ep_data = {
>  	.mode = PCI_MODE_EP,
>  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> +	.max_lanes = 1,
>  };
>  
>  static const struct of_device_id of_j721e_pcie_match[] = {
> @@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
>  	pcie->user_cfg_base = base;
>  
>  	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> -	if (ret || num_lanes > MAX_LANES)
> +	if (ret || num_lanes > data->max_lanes)
>  		num_lanes = 1;
>  	pcie->num_lanes = num_lanes;
>  
> -- 
> 2.38.GIT
> 

Re: [PATCH v5 1/4] PCI: j721e: Add per platform maximum lane settings

[Matt Ranostay]

On Thu, Nov 10, 2022 at 04:46:21PM +0100, Lorenzo Pieralisi wrote:
> On Wed, Nov 09, 2022 at 12:25:53AM -0800, Matt Ranostay wrote:
> > Various platforms have different maximum amount of lanes that
> > can be selected. Add max_lanes to struct j721e_pcie to allow
> > for error checking on num-lanes selection from device tree.
> 
> https://lore.kernel.org/linux-pci/CAL_JsqJ5cOLXhD-73esmhVwMEWGT+w3SJC14Z0jY4tQJQRA7iw@mail.gmail.com
> 
> Why have you reposted this patch ?
> 

Max lanes is still needed to calculate the bitmask (i.e. 2x needing one-bit mask, and 4x needing 2-bit mask), but
noticed that I should have change th commit message to be more clear, and drop the part of it being for device-tree
validation..

'PCI: j721e: Add warnings on num-lanes misconfiguration' could be dropped in the series if validation
should be done in the YAML schema checking.

- Matt

> Lorenzo
> 
> > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > ---
> >  drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
> >  1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > index a82f845cc4b5..875224d34958 100644
> > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > @@ -48,8 +48,6 @@ enum link_status {
> >  
> >  #define GENERATION_SEL_MASK		GENMASK(1, 0)
> >  
> > -#define MAX_LANES			2
> > -
> >  struct j721e_pcie {
> >  	struct cdns_pcie	*cdns_pcie;
> >  	struct clk		*refclk;
> > @@ -72,6 +70,7 @@ struct j721e_pcie_data {
> >  	unsigned int		quirk_disable_flr:1;
> >  	u32			linkdown_irq_regfield;
> >  	unsigned int		byte_access_allowed:1;
> > +	unsigned int		max_lanes;
> >  };
> >  
> >  static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
> > @@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
> >  	.quirk_retrain_flag = true,
> >  	.byte_access_allowed = false,
> >  	.linkdown_irq_regfield = LINK_DOWN,
> > +	.max_lanes = 2,
> >  };
> >  
> >  static const struct j721e_pcie_data j721e_pcie_ep_data = {
> >  	.mode = PCI_MODE_EP,
> >  	.linkdown_irq_regfield = LINK_DOWN,
> > +	.max_lanes = 2,
> >  };
> >  
> >  static const struct j721e_pcie_data j7200_pcie_rc_data = {
> > @@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
> >  	.quirk_detect_quiet_flag = true,
> >  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> >  	.byte_access_allowed = true,
> > +	.max_lanes = 2,
> >  };
> >  
> >  static const struct j721e_pcie_data j7200_pcie_ep_data = {
> >  	.mode = PCI_MODE_EP,
> >  	.quirk_detect_quiet_flag = true,
> >  	.quirk_disable_flr = true,
> > +	.max_lanes = 2,
> >  };
> >  
> >  static const struct j721e_pcie_data am64_pcie_rc_data = {
> >  	.mode = PCI_MODE_RC,
> >  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> >  	.byte_access_allowed = true,
> > +	.max_lanes = 1,
> >  };
> >  
> >  static const struct j721e_pcie_data am64_pcie_ep_data = {
> >  	.mode = PCI_MODE_EP,
> >  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> > +	.max_lanes = 1,
> >  };
> >  
> >  static const struct of_device_id of_j721e_pcie_match[] = {
> > @@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> >  	pcie->user_cfg_base = base;
> >  
> >  	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> > -	if (ret || num_lanes > MAX_LANES)
> > +	if (ret || num_lanes > data->max_lanes)
> >  		num_lanes = 1;
> >  	pcie->num_lanes = num_lanes;
> >  
> > -- 
> > 2.38.GIT
> > 

Re: [PATCH v5 1/4] PCI: j721e: Add per platform maximum lane settings

[Lorenzo Pieralisi]

On Thu, Nov 10, 2022 at 08:52:44AM -0800, Matt Ranostay wrote:
> On Thu, Nov 10, 2022 at 04:46:21PM +0100, Lorenzo Pieralisi wrote:
> > On Wed, Nov 09, 2022 at 12:25:53AM -0800, Matt Ranostay wrote:
> > > Various platforms have different maximum amount of lanes that
> > > can be selected. Add max_lanes to struct j721e_pcie to allow
> > > for error checking on num-lanes selection from device tree.
> > 
> > https://lore.kernel.org/linux-pci/CAL_JsqJ5cOLXhD-73esmhVwMEWGT+w3SJC14Z0jY4tQJQRA7iw@mail.gmail.com
> > 
> > Why have you reposted this patch ?
> > 
> 
> Max lanes is still needed to calculate the bitmask (i.e. 2x needing one-bit mask, and 4x needing 2-bit mask), but
> noticed that I should have change th commit message to be more clear, and drop the part of it being for device-tree
> validation..

Can you do it please and repost ?

> 'PCI: j721e: Add warnings on num-lanes misconfiguration' could be dropped in the series if validation
> should be done in the YAML schema checking.

Please drop it for next posting.

Thanks,
Lorenzo

> - Matt
> 
> > Lorenzo
> > 
> > > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > > ---
> > >  drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
> > >  1 file changed, 8 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > > index a82f845cc4b5..875224d34958 100644
> > > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > > @@ -48,8 +48,6 @@ enum link_status {
> > >  
> > >  #define GENERATION_SEL_MASK		GENMASK(1, 0)
> > >  
> > > -#define MAX_LANES			2
> > > -
> > >  struct j721e_pcie {
> > >  	struct cdns_pcie	*cdns_pcie;
> > >  	struct clk		*refclk;
> > > @@ -72,6 +70,7 @@ struct j721e_pcie_data {
> > >  	unsigned int		quirk_disable_flr:1;
> > >  	u32			linkdown_irq_regfield;
> > >  	unsigned int		byte_access_allowed:1;
> > > +	unsigned int		max_lanes;
> > >  };
> > >  
> > >  static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
> > > @@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
> > >  	.quirk_retrain_flag = true,
> > >  	.byte_access_allowed = false,
> > >  	.linkdown_irq_regfield = LINK_DOWN,
> > > +	.max_lanes = 2,
> > >  };
> > >  
> > >  static const struct j721e_pcie_data j721e_pcie_ep_data = {
> > >  	.mode = PCI_MODE_EP,
> > >  	.linkdown_irq_regfield = LINK_DOWN,
> > > +	.max_lanes = 2,
> > >  };
> > >  
> > >  static const struct j721e_pcie_data j7200_pcie_rc_data = {
> > > @@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
> > >  	.quirk_detect_quiet_flag = true,
> > >  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> > >  	.byte_access_allowed = true,
> > > +	.max_lanes = 2,
> > >  };
> > >  
> > >  static const struct j721e_pcie_data j7200_pcie_ep_data = {
> > >  	.mode = PCI_MODE_EP,
> > >  	.quirk_detect_quiet_flag = true,
> > >  	.quirk_disable_flr = true,
> > > +	.max_lanes = 2,
> > >  };
> > >  
> > >  static const struct j721e_pcie_data am64_pcie_rc_data = {
> > >  	.mode = PCI_MODE_RC,
> > >  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> > >  	.byte_access_allowed = true,
> > > +	.max_lanes = 1,
> > >  };
> > >  
> > >  static const struct j721e_pcie_data am64_pcie_ep_data = {
> > >  	.mode = PCI_MODE_EP,
> > >  	.linkdown_irq_regfield = J7200_LINK_DOWN,
> > > +	.max_lanes = 1,
> > >  };
> > >  
> > >  static const struct of_device_id of_j721e_pcie_match[] = {
> > > @@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> > >  	pcie->user_cfg_base = base;
> > >  
> > >  	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> > > -	if (ret || num_lanes > MAX_LANES)
> > > +	if (ret || num_lanes > data->max_lanes)
> > >  		num_lanes = 1;
> > >  	pcie->num_lanes = num_lanes;
> > >  
> > > -- 
> > > 2.38.GIT
> > > 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v5 2/4] PCI: j721e: Add PCIe 4x lane selection support

[Matt Ranostay]

Add support for setting of two-bit field that allows selection of 4x
lane PCIe which was previously limited to only 2x lanes.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 875224d34958..efd065bc0104 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -43,7 +43,6 @@ enum link_status {
 };
 
 #define J721E_MODE_RC			BIT(7)
-#define LANE_COUNT_MASK			BIT(8)
 #define LANE_COUNT(n)			((n) << 8)
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
@@ -53,6 +52,7 @@ struct j721e_pcie {
 	struct clk		*refclk;
 	u32			mode;
 	u32			num_lanes;
+	u32			max_lanes;
 	void __iomem		*user_cfg_base;
 	void __iomem		*intd_cfg_base;
 	u32			linkdown_irq_regfield;
@@ -206,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
 {
 	struct device *dev = pcie->cdns_pcie->dev;
 	u32 lanes = pcie->num_lanes;
+	u32 mask = GENMASK(8, 8);
 	u32 val = 0;
 	int ret;
 
+	if (pcie->max_lanes == 4)
+		mask = GENMASK(9, 8);
+
 	val = LANE_COUNT(lanes - 1);
-	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+	ret = regmap_update_bits(syscon, offset, mask, val);
 	if (ret)
 		dev_err(dev, "failed to set link count\n");
 
@@ -440,6 +444,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
 	if (ret || num_lanes > data->max_lanes)
 		num_lanes = 1;
+
+	pcie->max_lanes = data->max_lanes;
 	pcie->num_lanes = num_lanes;
 
 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
-- 
2.38.GIT

[PATCH v5 3/4] PCI: j721e: add j784s4 PCIe configuration

[Matt Ranostay]

Add PCIe configuration for j784s4 platform which has 4x lane support.

Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index efd065bc0104..83b8100afaff 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -331,6 +331,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
 	.max_lanes = 1,
 };
 
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+	.mode = PCI_MODE_RC,
+	.quirk_retrain_flag = true,
+	.is_intc_v1 = true,
+	.byte_access_allowed = false,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+	.mode = PCI_MODE_EP,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
 static const struct of_device_id of_j721e_pcie_match[] = {
 	{
 		.compatible = "ti,j721e-pcie-host",
@@ -356,6 +371,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
 		.compatible = "ti,am64-pcie-ep",
 		.data = &am64_pcie_ep_data,
 	},
+	{
+		.compatible = "ti,j784s4-pcie-host",
+		.data = &j784s4_pcie_rc_data,
+	},
+	{
+		.compatible = "ti,j784s4-pcie-ep",
+		.data = &j784s4_pcie_ep_data,
+	},
 	{},
 };
 
-- 
2.38.GIT

[PATCH v5 4/4] PCI: j721e: Add warnings on num-lanes misconfiguration

[Matt Ranostay]

Added dev_warn messages to alert of misconfigurations for incorrect number
of lanes setting, or the lack of one being defined.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 83b8100afaff..f6320ad75587 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -465,9 +465,16 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 	pcie->user_cfg_base = base;
 
 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
-	if (ret || num_lanes > data->max_lanes)
+	if (ret) {
+		dev_warn(dev, "no num-lanes defined, defaulting to 1\n");
 		num_lanes = 1;
+	}
 
+	if (num_lanes > data->max_lanes) {
+		dev_warn(dev, "defined num-lanes %u is greater than the allowed maximum of %u, defaulting to 1\n",
+			 num_lanes, data->max_lanes);
+		num_lanes = 1;
+	}
 	pcie->max_lanes = data->max_lanes;
 	pcie->num_lanes = num_lanes;
 
-- 
2.38.GIT