* [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible
@ 2023-01-18 11:17 Abel Vesa
2023-01-18 11:17 ` [PATCH v2 2/2] PCI: qcom: Add SM8550 PCIe support Abel Vesa
2023-01-18 13:04 ` [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Johan Hovold
0 siblings, 2 replies; 3+ messages in thread
From: Abel Vesa @ 2023-01-18 11:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Lorenzo Pieralisi,
Rob Herring, Krzysztof Wilczyński, Bjorn Helgaas,
Krzysztof Kozlowski, Manivannan Sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, Linux Kernel Mailing List
Add the SM8550 platform to the binding.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
The v1 was here:
https://lore.kernel.org/all/20221116123505.2760397-1-abel.vesa@linaro.org/
Changes since v1:
* Switched to single compatible for both PCIes (qcom,pcie-sm8550)
* dropped enable-gpios property
* dropped interconnects related properties, the power-domains properties
and resets related properties the sm8550 specific allOf:if:then
* dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific
allOf:if:then clock-names array and decreased the minItems and
maxItems for clocks property accordingly
.../devicetree/bindings/pci/qcom,pcie.yaml | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a5859bb3dc28..78e8babd11d9 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -34,6 +34,7 @@ properties:
- qcom,pcie-sm8250
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
+ - qcom,pcie-sm8550
- qcom,pcie-ipq6018
reg:
@@ -197,6 +198,7 @@ allOf:
- qcom,pcie-sm8250
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
+ - qcom,pcie-sm8550
then:
properties:
reg:
@@ -611,6 +613,40 @@ allOf:
items:
- const: pci # PCIe core reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sm8550
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 9
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre # Aggre NoC PCIe0 AXI clock
+ - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock
+ iommus:
+ maxItems: 1
+ iommu-map:
+ maxItems: 2
+ resets:
+ minItems: 1
+ maxItems: 2
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+ - const: pcie_1_link_down_reset # PCIe link down reset
+
- if:
properties:
compatible:
@@ -694,6 +730,7 @@ allOf:
- qcom,pcie-sm8250
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
+ - qcom,pcie-sm8550
then:
oneOf:
- properties:
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v2 2/2] PCI: qcom: Add SM8550 PCIe support
2023-01-18 11:17 [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
@ 2023-01-18 11:17 ` Abel Vesa
2023-01-18 13:04 ` [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Johan Hovold
1 sibling, 0 replies; 3+ messages in thread
From: Abel Vesa @ 2023-01-18 11:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Lorenzo Pieralisi,
Rob Herring, Krzysztof Wilczyński, Bjorn Helgaas,
Krzysztof Kozlowski, Manivannan Sadhasivam
Cc: linux-arm-msm, linux-pci, devicetree, Linux Kernel Mailing List
Add compatible for both PCIe found on SM8550.
Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
The v1 was here:
https://lore.kernel.org/all/20221116123505.2760397-2-abel.vesa@linaro.org/
Changes since v1:
* changed the subject line prefix for the patch to match the history,
like Bjorn Helgaas suggested.
* added Konrad's R-b tag
drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 77e5dc7b88ad..85988b3fd4f6 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 {
/* 6 clocks typically, 7 for sm8250 */
struct qcom_pcie_resources_2_7_0 {
- struct clk_bulk_data clks[12];
+ struct clk_bulk_data clks[13];
int num_clks;
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
@@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[idx++].id = "noc_aggr_4";
res->clks[idx++].id = "noc_aggr_south_sf";
res->clks[idx++].id = "cnoc_qx";
+ res->clks[idx++].id = "cnoc_pcie_sf_axi";
num_opt_clks = idx - num_clks;
res->num_clks = idx;
@@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
{ }
};
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible
2023-01-18 11:17 [PATCH v2 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
2023-01-18 11:17 ` [PATCH v2 2/2] PCI: qcom: Add SM8550 PCIe support Abel Vesa
@ 2023-01-18 13:04 ` Johan Hovold
1 sibling, 0 replies; 3+ messages in thread
From: Johan Hovold @ 2023-01-18 13:04 UTC (permalink / raw)
To: Abel Vesa
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Lorenzo Pieralisi,
Rob Herring, Krzysztof Wilczyński, Bjorn Helgaas,
Krzysztof Kozlowski, Manivannan Sadhasivam, linux-arm-msm,
linux-pci, devicetree, Linux Kernel Mailing List
On Wed, Jan 18, 2023 at 01:17:03PM +0200, Abel Vesa wrote:
> Add the SM8550 platform to the binding.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>
> The v1 was here:
> https://lore.kernel.org/all/20221116123505.2760397-1-abel.vesa@linaro.org/
>
> Changes since v1:
> * Switched to single compatible for both PCIes (qcom,pcie-sm8550)
> * dropped enable-gpios property
> * dropped interconnects related properties, the power-domains properties
> and resets related properties the sm8550 specific allOf:if:then
> * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific
> allOf:if:then clock-names array and decreased the minItems and
> maxItems for clocks property accordingly
>
> .../devicetree/bindings/pci/qcom,pcie.yaml | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index a5859bb3dc28..78e8babd11d9 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -34,6 +34,7 @@ properties:
> - qcom,pcie-sm8250
> - qcom,pcie-sm8450-pcie0
> - qcom,pcie-sm8450-pcie1
> + - qcom,pcie-sm8550
> - qcom,pcie-ipq6018
>
> reg:
> @@ -197,6 +198,7 @@ allOf:
> - qcom,pcie-sm8250
> - qcom,pcie-sm8450-pcie0
> - qcom,pcie-sm8450-pcie1
> + - qcom,pcie-sm8550
> then:
> properties:
> reg:
> @@ -611,6 +613,40 @@ allOf:
> items:
> - const: pci # PCIe core reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-sm8550
> + then:
> + properties:
> + clocks:
> + minItems: 8
> + maxItems: 9
> + clock-names:
> + items:
> + - const: pipe # PIPE clock
The pipe clock is managed by the PHY and should not be here either.
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: ddrss_sf_tbu # PCIe SF TBU clock
> + - const: aggre # Aggre NoC PCIe0 AXI clock
The comment referring to a specific controller instance (PCIe0) looks
wrong.
We used a noc_ prefix to separate it from the cnoc_ clocks for sc8280xp
(e.g. noc_aggr_4).
> + - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock
The _pcie infix looks unnecessary, same comment about PCIe1 as above.
> + iommus:
> + maxItems: 1
> + iommu-map:
> + maxItems: 2
> + resets:
> + minItems: 1
> + maxItems: 2
> + reset-names:
> + items:
> + - const: pci # PCIe core reset
> + - const: pcie_1_link_down_reset # PCIe link down reset
No need to repeat the resource type in the name. Shouldn't this just be
'link_down' or similar?
> +
> - if:
> properties:
> compatible:
> @@ -694,6 +730,7 @@ allOf:
> - qcom,pcie-sm8250
> - qcom,pcie-sm8450-pcie0
> - qcom,pcie-sm8450-pcie1
> + - qcom,pcie-sm8550
> then:
> oneOf:
> - properties:
Johan
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-01-18 13:36 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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