linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com,
	krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, quic_srichara@quicinc.com,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v5 15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
Date: Thu, 16 Mar 2023 13:41:13 +0530	[thread overview]
Message-ID: <20230316081117.14288-16-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230316081117.14288-1-manivannan.sadhasivam@linaro.org>

"mhi" register region contains the MHI registers that could be used by
the PCIe controller drivers to get debug information like PCIe link
transition counts on newer SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index fb32c43dd12d..ecbb0f9efa21 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -44,11 +44,11 @@ properties:
 
   reg:
     minItems: 4
-    maxItems: 5
+    maxItems: 6
 
   reg-names:
     minItems: 4
-    maxItems: 5
+    maxItems: 6
 
   interrupts:
     minItems: 1
@@ -185,13 +185,15 @@ allOf:
       properties:
         reg:
           minItems: 4
-          maxItems: 4
+          maxItems: 5
         reg-names:
+          minItems: 4
           items:
             - const: parf # Qualcomm specific registers
             - const: dbi # DesignWare PCIe registers
             - const: elbi # External local bus interface registers
             - const: config # PCIe configuration space
+            - const: mhi # MHI registers
 
   - if:
       properties:
@@ -209,14 +211,16 @@ allOf:
       properties:
         reg:
           minItems: 5
-          maxItems: 5
+          maxItems: 6
         reg-names:
+          minItems: 5
           items:
             - const: parf # Qualcomm specific registers
             - const: dbi # DesignWare PCIe registers
             - const: elbi # External local bus interface registers
             - const: atu # ATU address space
             - const: config # PCIe configuration space
+            - const: mhi # MHI registers
 
   - if:
       properties:
-- 
2.25.1


  parent reply	other threads:[~2023-03-16  8:13 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-16  8:10 [PATCH v5 00/19] Qcom PCIe cleanups and improvements Manivannan Sadhasivam
2023-03-16  8:10 ` [PATCH v5 01/19] PCI: qcom: Fix the incorrect register usage in v2.7.0 config Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 02/19] PCI: qcom: Remove PCIE20_ prefix from register definitions Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 03/19] PCI: qcom: Sort and group registers and bitfield definitions Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 04/19] PCI: qcom: Use bitfield definitions for register fields Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 05/19] PCI: qcom: Add missing macros " Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 06/19] PCI: qcom: Use lower case for hex Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 07/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 10/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 11/19] PCI: qcom: Use bulk reset APIs for handling resets " Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 12/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 13/19] PCI: qcom: Use macros for defining total no. of clocks & supplies Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 14/19] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version Manivannan Sadhasivam
2023-03-16  8:11 ` Manivannan Sadhasivam [this message]
2023-03-16  8:11 ` [PATCH v5 16/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 17/19] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 18/19] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2023-03-16  8:11 ` [PATCH v5 19/19] PCI: qcom: Expose link transition counts via debugfs Manivannan Sadhasivam
2023-04-05  4:09 ` (subset) [PATCH v5 00/19] Qcom PCIe cleanups and improvements Bjorn Andersson
2023-04-11  9:34 ` Lorenzo Pieralisi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230316081117.14288-16-manivannan.sadhasivam@linaro.org \
    --to=manivannan.sadhasivam@linaro.org \
    --cc=andersson@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=konrad.dybcio@linaro.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=kw@linux.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=quic_srichara@quicinc.com \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).