From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com,
krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_srichara@quicinc.com,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v5 04/19] PCI: qcom: Use bitfield definitions for register fields
Date: Thu, 16 Mar 2023 13:41:02 +0530 [thread overview]
Message-ID: <20230316081117.14288-5-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230316081117.14288-1-manivannan.sadhasivam@linaro.org>
To maintain uniformity throughout the driver and also to make the code
easier to read, let's make use of bitfield definitions for register fields.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index a33653d576b6..44c31c65695a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -76,24 +76,24 @@
#define REQ_NOT_ENTR_L1 BIT(5)
/* PARF_PCS_DEEMPH register fields */
-#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
-#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
-#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
/* PARF_PCS_SWING register fields */
-#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
-#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
+#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
+#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
/* PARF_PHY_CTRL register fields */
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
-#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
/* PARF_PHY_REFCLK register fields */
#define PHY_REFCLK_SSP_EN BIT(16)
#define PHY_REFCLK_USE_PAD BIT(12)
/* PARF_CONFIG_BITS register fields */
-#define PHY_RX0_EQ(x) ((x) << 24)
+#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
/* PARF_SLV_ADDR_SPACE_SIZE register value */
#define SLV_ADDR_SPACE_SZ 0x10000000
--
2.25.1
next prev parent reply other threads:[~2023-03-16 8:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-16 8:10 [PATCH v5 00/19] Qcom PCIe cleanups and improvements Manivannan Sadhasivam
2023-03-16 8:10 ` [PATCH v5 01/19] PCI: qcom: Fix the incorrect register usage in v2.7.0 config Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 02/19] PCI: qcom: Remove PCIE20_ prefix from register definitions Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 03/19] PCI: qcom: Sort and group registers and bitfield definitions Manivannan Sadhasivam
2023-03-16 8:11 ` Manivannan Sadhasivam [this message]
2023-03-16 8:11 ` [PATCH v5 05/19] PCI: qcom: Add missing macros for register fields Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 06/19] PCI: qcom: Use lower case for hex Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 07/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 10/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 11/19] PCI: qcom: Use bulk reset APIs for handling resets " Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 12/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 13/19] PCI: qcom: Use macros for defining total no. of clocks & supplies Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 14/19] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 16/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 17/19] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 18/19] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 19/19] PCI: qcom: Expose link transition counts via debugfs Manivannan Sadhasivam
2023-04-05 4:09 ` (subset) [PATCH v5 00/19] Qcom PCIe cleanups and improvements Bjorn Andersson
2023-04-11 9:34 ` Lorenzo Pieralisi
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