From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com,
krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_srichara@quicinc.com,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v5 05/19] PCI: qcom: Add missing macros for register fields
Date: Thu, 16 Mar 2023 13:41:03 +0530 [thread overview]
Message-ID: <20230316081117.14288-6-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230316081117.14288-1-manivannan.sadhasivam@linaro.org>
Some of the registers are changed using hardcoded bitfields without macros.
This provides no information on what the register setting is about. So add
the macros to those fields for making the code more understandable.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++-----------
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 44c31c65695a..f48990ac86dd 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -63,6 +63,7 @@
#define MISC_CONTROL_1_REG 0x8BC
/* PARF_SYS_CTRL register fields */
+#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
#define MST_WAKEUP_EN BIT(13)
#define SLV_WAKEUP_EN BIT(12)
#define MSTR_ACLK_CGC_DIS BIT(10)
@@ -87,6 +88,7 @@
/* PARF_PHY_CTRL register fields */
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
+#define PHY_TEST_PWR_DOWN BIT(0)
/* PARF_PHY_REFCLK register fields */
#define PHY_REFCLK_SSP_EN BIT(16)
@@ -103,6 +105,12 @@
#define MSTR_AXI_CLK_EN BIT(1)
#define BYPASS BIT(4)
+/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
+#define EN BIT(31)
+
+/* PARF_LTSSM register fields */
+#define LTSSM_EN BIT(8)
+
/* PARF_DEVICE_TYPE register fields */
#define DEVICE_TYPE_RC 0x4
@@ -440,7 +448,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PARF_PHY_CTRL);
- val &= ~BIT(0);
+ val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
@@ -595,7 +603,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
if (IS_ENABLED(CONFIG_PCI_MSI)) {
u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
- val |= BIT(31);
+ val |= EN;
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
}
@@ -608,7 +616,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
/* enable link training */
val = readl(pcie->parf + PARF_LTSSM);
- val |= BIT(8);
+ val |= LTSSM_EN;
writel(val, pcie->parf + PARF_LTSSM);
}
@@ -715,7 +723,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PARF_PHY_CTRL);
- val &= ~BIT(0);
+ val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
/* change DBI base address */
@@ -723,15 +731,15 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
/* MAC PHY_POWERDOWN MUX DISABLE */
val = readl(pcie->parf + PARF_SYS_CTRL);
- val &= ~BIT(29);
+ val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
writel(val, pcie->parf + PARF_SYS_CTRL);
val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
- val |= BIT(4);
+ val |= BYPASS;
writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
- val |= BIT(31);
+ val |= EN;
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
return 0;
@@ -994,7 +1002,7 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PARF_PHY_CTRL);
- val &= ~BIT(0);
+ val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
/* change DBI base address */
@@ -1002,15 +1010,15 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)
/* MAC PHY_POWERDOWN MUX DISABLE */
val = readl(pcie->parf + PARF_SYS_CTRL);
- val &= ~BIT(29);
+ val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
writel(val, pcie->parf + PARF_SYS_CTRL);
val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
- val |= BIT(4);
+ val |= BYPASS;
writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
- val |= BIT(31);
+ val |= EN;
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
return 0;
@@ -1159,7 +1167,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
val = readl(pcie->parf + PARF_PHY_CTRL);
- val &= ~BIT(0);
+ val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
@@ -1275,7 +1283,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PARF_PHY_CTRL);
- val &= ~BIT(0);
+ val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
/* change DBI base address */
@@ -1283,11 +1291,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
/* MAC PHY_POWERDOWN MUX DISABLE */
val = readl(pcie->parf + PARF_SYS_CTRL);
- val &= ~BIT(29);
+ val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
writel(val, pcie->parf + PARF_SYS_CTRL);
val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
- val |= BIT(4);
+ val |= BYPASS;
writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
/* Enable L1 and L1SS */
@@ -1296,7 +1304,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
writel(val, pcie->parf + PARF_PM_CTRL);
val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
- val |= BIT(31);
+ val |= EN;
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
return 0;
@@ -1388,7 +1396,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
val = readl(pcie->parf + PARF_PHY_CTRL);
- val &= ~BIT(0);
+ val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
--
2.25.1
next prev parent reply other threads:[~2023-03-16 8:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-16 8:10 [PATCH v5 00/19] Qcom PCIe cleanups and improvements Manivannan Sadhasivam
2023-03-16 8:10 ` [PATCH v5 01/19] PCI: qcom: Fix the incorrect register usage in v2.7.0 config Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 02/19] PCI: qcom: Remove PCIE20_ prefix from register definitions Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 03/19] PCI: qcom: Sort and group registers and bitfield definitions Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 04/19] PCI: qcom: Use bitfield definitions for register fields Manivannan Sadhasivam
2023-03-16 8:11 ` Manivannan Sadhasivam [this message]
2023-03-16 8:11 ` [PATCH v5 06/19] PCI: qcom: Use lower case for hex Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 07/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 10/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 11/19] PCI: qcom: Use bulk reset APIs for handling resets " Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 12/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 13/19] PCI: qcom: Use macros for defining total no. of clocks & supplies Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 14/19] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 16/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 17/19] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 18/19] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2023-03-16 8:11 ` [PATCH v5 19/19] PCI: qcom: Expose link transition counts via debugfs Manivannan Sadhasivam
2023-04-05 4:09 ` (subset) [PATCH v5 00/19] Qcom PCIe cleanups and improvements Bjorn Andersson
2023-04-11 9:34 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230316081117.14288-6-manivannan.sadhasivam@linaro.org \
--to=manivannan.sadhasivam@linaro.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=quic_srichara@quicinc.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).