From: Niklas Cassel <cassel@kernel.org>
To: "Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Niklas Cassel" <cassel@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Damien Le Moal" <dlemoal@kernel.org>,
"Jon Lin" <jon.lin@rock-chips.com>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Simon Xue" <xxm@rock-chips.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org
Subject: [PATCH v3 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs
Date: Wed, 08 May 2024 15:13:34 +0200 [thread overview]
Message-ID: <20240508-rockchip-pcie-ep-v1-v3-3-1748e202b084@kernel.org> (raw)
In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org>
The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd
that are triggered when the PCIe controller (when running in Endpoint mode)
has sent an Assert_INTA Message to the upstream device.
Some DWC controllers have these interrupt in a combined interrupt signal.
Add the description of these interrupts to the device tree binding.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index f5f12cbc2cb3..f474b9e3fc7e 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -151,6 +151,15 @@ properties:
Application-specific IRQ raised depending on the vendor-specific
events basis.
const: app
+ - description:
+ Interrupts triggered when the controller itself (in Endpoint mode)
+ has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to
+ the upstream device.
+ pattern: "^tx_int(a|b|c|d)$"
+ - description:
+ Combined interrupt signal raised when the controller has sent an
+ Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details.
+ const: legacy
- description:
Vendor-specific IRQ names. Consider using the generic names above
for new bindings.
--
2.44.0
next prev parent reply other threads:[~2024-05-08 13:13 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 13:13 [PATCH v3 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Niklas Cassel
2024-05-08 13:13 ` Niklas Cassel [this message]
2024-05-08 13:13 ` [PATCH v3 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 07/13] PCI: dw-rockchip: Fix weird indentation Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 10/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588 Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Niklas Cassel
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