[PATCH] PCI: designware: Fix configuration base address

[PATCH] PCI: designware: Fix configuration base address

[Minghuan Lian]

The code has calculated cfg0_base and cfg1_base when parsing 'reg'
or 'ranges' property of PCI DTS node. so remove duplicate calculation.
And when using 'reg', resource cfg is not used, the removed code
will get incorrect configuration base.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index c28ca05..0f3cb2a 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	pp->mem_base = pp->mem.start;
 
 	if (!pp->va_cfg0_base) {
-		pp->cfg0_base = pp->cfg.start;
 		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
 						pp->cfg0_size);
 		if (!pp->va_cfg0_base) {
@@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	}
 
 	if (!pp->va_cfg1_base) {
-		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
 		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
 						pp->cfg1_size);
 		if (!pp->va_cfg1_base) {
-- 
1.9.1

[PATCH] PCI: designware: Fix IO resource end address calculation

[Minghuan Lian]

End address should be equal to start_addr + size - 1.
The patch fixes PCI IO resource end address calculation.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 0f3cb2a..c19184f7 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 			pp->io.end = min_t(resource_size_t,
 					   IO_SPACE_LIMIT,
 					   range.pci_addr + range.size
-					   + global_io_offset);
+					   + global_io_offset - 1);
 			pp->io_size = resource_size(&pp->io);
 			pp->io_bus_addr = range.pci_addr;
 			pp->io_base = range.cpu_addr;
-- 
1.9.1

[PATCH v3 1/3] PCI: designware: Rename get_msi_data to get_msi_addr

[Minghuan Lian]

The function get_msi_data is used to return MSI message address.
In order to accurately express function purpose the patch rename
it to get_msi_addr.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 4 ++--
 drivers/pci/host/pcie-designware.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 5d720c2..1c09f814 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	 */
 	desc->msi_attrib.multiple = msgvec;
 
-	if (pp->ops->get_msi_data)
-		msg.address_lo = pp->ops->get_msi_data(pp);
+	if (pp->ops->get_msi_addr)
+		msg.address_lo = pp->ops->get_msi_addr(pp);
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 48f8670..904e40a 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -70,7 +70,7 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
-	u32 (*get_msi_data)(struct pcie_port *pp);
+	u32 (*get_msi_addr)(struct pcie_port *pp);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
-- 
1.9.1

[PATCH v3 2/3] PCI: designware: Add get_msi_data() to pcie_host_ops

[Minghuan Lian]

The patch adds get_msi_data() for some platforms to return their
special MSI message data.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 7 ++++++-
 drivers/pci/host/pcie-designware.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 1c09f814..c28ca05 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -366,7 +366,12 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
-	msg.data = pos;
+
+	if (pp->ops->get_msi_data)
+		msg.data = pp->ops->get_msi_data(pp, pos);
+	else
+		msg.data = pos;
+
 	write_msi_msg(irq, &msg);
 
 	return 0;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 904e40a..c625675 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -71,6 +71,7 @@ struct pcie_host_ops {
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
 	u32 (*get_msi_addr)(struct pcie_port *pp);
+	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
-- 
1.9.1

[PATCH v3 3/3] PCI: Layerscape: Add Layerscape PCIe driver

[Minghuan Lian]

Add support for Freescale Layerscape PCIe controller. This driver
re-uses the designware core code.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
Change log:
v3:
1. Add prefechable mem region and adjust mem region
2. Rename 'pcie-scfg' to 'fsl,pcie-scfg'
3. Change MSI interrupt handler
4. Use module_platform_driver_probe instead of subsys_initcall

v2:
1. Add pcie-scfg to link scfg device node and remove "fsl, ls-pcie" compatible
2. Use regmap API to access scfg.
3. remove ls1021 PCI device ID.
4. remove unused irq pme_irq and ls_pcie_list.
5. Do not set scfg bit reverse mode

 .../devicetree/bindings/pci/layerscape-pci.txt     |  46 ++++
 drivers/pci/host/Kconfig                           |   7 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pci-layerscape.c                  | 274 +++++++++++++++++++++
 4 files changed, 328 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt
 create mode 100644 drivers/pci/host/pci-layerscape.c

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
new file mode 100644
index 0000000..d7b0026
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -0,0 +1,46 @@
+Freescale Layerscape PCIe controller
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- reg: base addresses and lengths of the PCIe controller
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+  "intr": The interrupt that is asserted for controller interrupts
+  "msi": The interrupt that is asserted when an MSI is received
+  "pme": The interrupt that is asserted when PME state changes
+- fsl,pcie-scfg: Must include two entries.
+  The first entry must be a link to the SCFG device node
+  The second entry must be '0' or '1' based on physical PCIe controller index.
+  used to get SCFG PEXN registers
+
+Example:
+
+	pcie@3400000 {
+		compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
+		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */
+			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+		interrupt-names = "intr", "msi", "pme";
+		fsl,pcie-scfg = <&scfg 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
+			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
+				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+	};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 34134d6..7c49456 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -82,4 +82,11 @@ config PCIE_XILINX
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
 	  Host Bridge driver.
 
+config PCI_LAYERSCAPE
+	bool "Freescale Layerscape PCIe controller"
+	select PCIE_DW
+	select MFD_SYSCON
+	help
+	  Say Y here if you want PCIe controller support on Layerscape SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 182929c..fd10554 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
+obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
new file mode 100644
index 0000000..8f5e65e
--- /dev/null
+++ b/drivers/pci/host/pci-layerscape.c
@@ -0,0 +1,274 @@
+/*
+ * PCIe host controller driver for Freescale Layerscape SoCs
+ *
+ * Copyright (C) 2014 Freescale Semiconductor.
+ *
+  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/bitrev.h>
+
+#include "pcie-designware.h"
+
+/* PEX1/2 Misc Ports Status Register */
+#define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
+#define LTSSM_STATE_SHIFT	20
+#define LTSSM_STATE_MASK	0x3f
+#define LTSSM_PCIE_L0		0x11 /* L0 state */
+
+/* SCFG MSI register */
+#define SCFG_SPIMSICR		0x40
+#define SCFG_SPIMSICLRCR	0x90
+
+#define MSI_LS1021A_ADDR		0x1570040
+#define MSI_LS1021A_DATA(pex_idx)	(0xb3 + pex_idx)
+
+/* Symbol Timer Register and Filter Mask Register 1 */
+#define PCIE_STRFMR1 0x71c
+
+struct ls_pcie {
+	struct list_head node;
+	struct device *dev;
+	struct pci_bus *bus;
+	void __iomem *dbi;
+	struct regmap *scfg;
+	struct pcie_port pp;
+	int index;
+	int msi_irq;
+};
+
+#define to_ls_pcie(x)	container_of(x, struct ls_pcie, pp)
+
+static int ls_pcie_link_up(struct pcie_port *pp)
+{
+	u32 state;
+	struct ls_pcie *pcie = to_ls_pcie(pp);
+
+	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
+	state = bitrev32(state);
+	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
+
+	if (state < LTSSM_PCIE_L0)
+		return 0;
+
+	return 1;
+}
+
+static u32 ls_pcie_get_msi_addr(struct pcie_port *pp)
+{
+	return MSI_LS1021A_ADDR;
+}
+
+static u32 ls_pcie_get_msi_data(struct pcie_port *pp, int pos)
+{
+	struct ls_pcie *pcie = to_ls_pcie(pp);
+
+	return MSI_LS1021A_DATA(pcie->index);
+}
+
+static irqreturn_t ls_pcie_msi_irq_handler(int irq, void *data)
+{
+	struct pcie_port *pp = data;
+	struct ls_pcie *pcie = to_ls_pcie(pp);
+	unsigned int msi_irq;
+
+	/* clear the interrupt */
+	regmap_write(pcie->scfg, SCFG_SPIMSICLRCR,
+		     MSI_LS1021A_DATA(pcie->index));
+
+	msi_irq = irq_find_mapping(pp->irq_domain, 0);
+	if (!msi_irq) {
+		/*
+		 * that's weird who triggered this?
+		 * just clear it
+		 */
+		dev_err(pcie->dev, "unexpected MSI\n");
+		return IRQ_NONE;
+	}
+
+	generic_handle_irq(msi_irq);
+	return IRQ_HANDLED;
+}
+
+static void ls_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
+{
+}
+
+static void ls_pcie_msi_set_irq(struct pcie_port *pp, int irq)
+{
+}
+
+static void ls1021a_pcie_msi_fixup(struct pcie_port *pp)
+{
+	int i;
+
+	/*
+	 * LS1021A has only one MSI interrupt
+	 * Set all msi interrupts as used except the first one
+	 */
+	for (i = 1; i < MAX_MSI_IRQS; i++)
+		set_bit(i, pp->msi_irq_in_use);
+}
+
+static void ls_pcie_host_init(struct pcie_port *pp)
+{
+	struct ls_pcie *pcie = to_ls_pcie(pp);
+	int count = 0;
+	u32 val;
+
+	dw_pcie_setup_rc(pp);
+
+	while (!ls_pcie_link_up(pp)) {
+		usleep_range(100, 1000);
+		count++;
+		if (count >= 200) {
+			dev_err(pp->dev, "phy link never came up\n");
+			return;
+		}
+	}
+
+	if (of_device_is_compatible(pcie->dev->of_node, "fsl,ls1021a-pcie")) {
+		/*
+		 * LS1021A Workaround for internal TKT228622
+		 * to fix the INTx hang issue
+		 */
+		val = ioread32(pcie->dbi + PCIE_STRFMR1);
+		val &= 0xffff;
+		iowrite32(val, pcie->dbi + PCIE_STRFMR1);
+
+		ls1021a_pcie_msi_fixup(pp);
+	}
+}
+
+static struct pcie_host_ops ls_pcie_host_ops = {
+	.link_up = ls_pcie_link_up,
+	.host_init = ls_pcie_host_init,
+	.msi_set_irq = ls_pcie_msi_set_irq,
+	.msi_clear_irq = ls_pcie_msi_clear_irq,
+	.get_msi_addr = ls_pcie_get_msi_addr,
+	.get_msi_data = ls_pcie_get_msi_data,
+};
+
+static int ls_add_pcie_port(struct ls_pcie *pcie)
+{
+	struct pcie_port *pp;
+	int ret;
+
+	if (!pcie)
+		return -EINVAL;
+
+	pp = &pcie->pp;
+	pp->dev = pcie->dev;
+	pp->dbi_base = pcie->dbi;
+	pp->msi_irq = pcie->msi_irq;
+
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		ret = devm_request_irq(pp->dev, pp->msi_irq,
+					ls_pcie_msi_irq_handler,
+					IRQF_SHARED, "ls-pcie-msi", pp);
+		if (ret) {
+			dev_err(pp->dev, "failed to request msi irq\n");
+			return ret;
+		}
+	}
+
+	pp->root_bus_nr = -1;
+	pp->ops = &ls_pcie_host_ops;
+
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(pp->dev, "failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __init ls_pcie_probe(struct platform_device *pdev)
+{
+	struct ls_pcie *pcie;
+	struct resource *dbi_base;
+	u32 index[2];
+	int ret;
+
+	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pcie->dev = &pdev->dev;
+
+	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+	if (!dbi_base) {
+		dev_err(&pdev->dev, "missing *regs* space\n");
+		return -ENODEV;
+	}
+
+	pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
+	if (IS_ERR(pcie->dbi))
+		return PTR_ERR(pcie->dbi);
+
+	pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+						     "fsl,pcie-scfg");
+	if (IS_ERR(pcie->scfg)) {
+		dev_err(&pdev->dev, "No syscfg phandle specified\n");
+		return PTR_ERR(pcie->scfg);
+	}
+
+	ret = of_property_read_u32_array(pdev->dev.of_node,
+					 "fsl,pcie-scfg", index, 2);
+	if (ret)
+		return ret;
+	pcie->index = index[1];
+
+	pcie->msi_irq = platform_get_irq_byname(pdev, "msi");
+	if (pcie->msi_irq < 0) {
+		dev_err(&pdev->dev,
+			"failed to get MSI IRQ: %d\n", pcie->msi_irq);
+		return pcie->msi_irq;
+	}
+
+	ret = ls_add_pcie_port(pcie);
+	if (ret < 0)
+		return ret;
+
+	platform_set_drvdata(pdev, pcie);
+
+	return 0;
+}
+
+static const struct of_device_id ls_pcie_of_match[] = {
+	{ .compatible = "fsl,ls1021a-pcie" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
+
+static struct platform_driver ls_pcie_driver = {
+	.driver = {
+		.name = "layerscape-pcie",
+		.owner = THIS_MODULE,
+		.of_match_table = ls_pcie_of_match,
+	},
+};
+
+module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
+
+MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
+MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

Re: [PATCH v3 3/3] PCI: Layerscape: Add Layerscape PCIe driver

[Scott Wood]

On Tue, 2014-09-23 at 22:29 +0800, Minghuan Lian wrote:
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 34134d6..7c49456 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -82,4 +82,11 @@ config PCIE_XILINX
>  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
>  	  Host Bridge driver.
>  
> +config PCI_LAYERSCAPE
> +	bool "Freescale Layerscape PCIe controller"
> +	select PCIE_DW
> +	select MFD_SYSCON
> +	help
> +	  Say Y here if you want PCIe controller support on Layerscape SoCs.
> +
>  endmenu

Are you sure there are no dependencies for this to build?  At the least
you need OF.

I think you should also be selecting REGMAP.

-Scott

Re: [PATCH v3 1/3] PCI: designware: Rename get_msi_data to get_msi_addr

[Bjorn Helgaas]

[+cc Mohit, Jingoo]

On Tue, Sep 23, 2014 at 10:28:58PM +0800, Minghuan Lian wrote:
> The function get_msi_data is used to return MSI message address.
> In order to accurately express function purpose the patch rename
> it to get_msi_addr.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

I think this looks like a good idea, but it needs an ack from Mohit and/or
Jingoo (cc'd).

You previously asked whether .get_msi_addr() should also be changed to
return u64 instead of u32.  I think it should, and you can do that in a
separate patch that also changes the use in dw_msi_setup_irq() to split the
64-bit result into msg.address_lo and msg.address_hi.

I don't see any implementations of .get_msi_data() or .get_msi_addr(), so 
this seems pretty straightforward.

Bjorn

> ---
> Change log:
> v3: no change
> v2: no change just derived from v1
> 
>  drivers/pci/host/pcie-designware.c | 4 ++--
>  drivers/pci/host/pcie-designware.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 5d720c2..1c09f814 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
>  	 */
>  	desc->msi_attrib.multiple = msgvec;
>  
> -	if (pp->ops->get_msi_data)
> -		msg.address_lo = pp->ops->get_msi_data(pp);
> +	if (pp->ops->get_msi_addr)
> +		msg.address_lo = pp->ops->get_msi_addr(pp);
>  	else
>  		msg.address_lo = virt_to_phys((void *)pp->msi_data);
>  	msg.address_hi = 0x0;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index 48f8670..904e40a 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -70,7 +70,7 @@ struct pcie_host_ops {
>  	void (*host_init)(struct pcie_port *pp);
>  	void (*msi_set_irq)(struct pcie_port *pp, int irq);
>  	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
> -	u32 (*get_msi_data)(struct pcie_port *pp);
> +	u32 (*get_msi_addr)(struct pcie_port *pp);
>  	void (*scan_bus)(struct pcie_port *pp);
>  	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
>  };
> -- 
> 1.9.1
> 

Re: [PATCH] PCI: designware: Fix configuration base address

[Bjorn Helgaas]

[+cc Mohit, Jingoo]

On Tue, Sep 23, 2014 at 10:28:56PM +0800, Minghuan Lian wrote:
> The code has calculated cfg0_base and cfg1_base when parsing 'reg'
> or 'ranges' property of PCI DTS node. so remove duplicate calculation.
> And when using 'reg', resource cfg is not used, the removed code
> will get incorrect configuration base.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
>  drivers/pci/host/pcie-designware.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index c28ca05..0f3cb2a 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  	pp->mem_base = pp->mem.start;
>  
>  	if (!pp->va_cfg0_base) {
> -		pp->cfg0_base = pp->cfg.start;
>  		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
>  						pp->cfg0_size);
>  		if (!pp->va_cfg0_base) {
> @@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  	}
>  
>  	if (!pp->va_cfg1_base) {
> -		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
>  		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
>  						pp->cfg1_size);
>  		if (!pp->va_cfg1_base) {
> -- 
> 1.9.1
> 

Re: [PATCH] PCI: designware: Fix IO resource end address calculation

[Bjorn Helgaas]

[+cc Mohit, Jingoo]

On Tue, Sep 23, 2014 at 10:28:57PM +0800, Minghuan Lian wrote:
> End address should be equal to start_addr + size - 1.
> The patch fixes PCI IO resource end address calculation.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
>  drivers/pci/host/pcie-designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 0f3cb2a..c19184f7 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  			pp->io.end = min_t(resource_size_t,
>  					   IO_SPACE_LIMIT,
>  					   range.pci_addr + range.size
> -					   + global_io_offset);
> +					   + global_io_offset - 1);
>  			pp->io_size = resource_size(&pp->io);
>  			pp->io_bus_addr = range.pci_addr;
>  			pp->io_base = range.cpu_addr;
> -- 
> 1.9.1
> 

Re: [PATCH v3 2/3] PCI: designware: Add get_msi_data() to pcie_host_ops

[Bjorn Helgaas]

[+cc Mohit, Jingoo]

On Tue, Sep 23, 2014 at 10:28:59PM +0800, Minghuan Lian wrote:
> The patch adds get_msi_data() for some platforms to return their
> special MSI message data.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> Change log:
> v3: no change
> v2: no change just derived from v1
> 
>  drivers/pci/host/pcie-designware.c | 7 ++++++-
>  drivers/pci/host/pcie-designware.h | 1 +
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 1c09f814..c28ca05 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -366,7 +366,12 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
>  	else
>  		msg.address_lo = virt_to_phys((void *)pp->msi_data);
>  	msg.address_hi = 0x0;
> -	msg.data = pos;
> +
> +	if (pp->ops->get_msi_data)
> +		msg.data = pp->ops->get_msi_data(pp, pos);
> +	else
> +		msg.data = pos;
> +
>  	write_msi_msg(irq, &msg);
>  
>  	return 0;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index 904e40a..c625675 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -71,6 +71,7 @@ struct pcie_host_ops {
>  	void (*msi_set_irq)(struct pcie_port *pp, int irq);
>  	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
>  	u32 (*get_msi_addr)(struct pcie_port *pp);
> +	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
>  	void (*scan_bus)(struct pcie_port *pp);
>  	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
>  };
> -- 
> 1.9.1
> 

Re: [PATCH v3 3/3] PCI: Layerscape: Add Layerscape PCIe driver

[Lian Minghuan-B31939]

Hi Scott,

Please see my comments inline.

On 2014年09月24日 05:25, Scott Wood wrote:
> On Tue, 2014-09-23 at 22:29 +0800, Minghuan Lian wrote:
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index 34134d6..7c49456 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -82,4 +82,11 @@ config PCIE_XILINX
>>   	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
>>   	  Host Bridge driver.
>>   
>> +config PCI_LAYERSCAPE
>> +	bool "Freescale Layerscape PCIe controller"
>> +	select PCIE_DW
>> +	select MFD_SYSCON
>> +	help
>> +	  Say Y here if you want PCIe controller support on Layerscape SoCs.
>> +
>>   endmenu
> Are you sure there are no dependencies for this to build?  At the least
> you need OF.
>
> I think you should also be selecting REGMAP.
[Minghuan] Yes, it does need OF. I will add 'depends on OF' next version.
Because MFS_SYSCON will select REGMAP, so I think it is enough to select 
MFS_SYSCON.

> -Scott
>
>

RE: [PATCH v3 1/3] PCI: designware: Rename get_msi_data to get_msi_addr

[Mohit KUMAR DCG]

Hello Minghuan,

> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Wednesday, September 24, 2014 4:16 AM
> To: Minghuan Lian
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Zang
> Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd
> Bergmann; Mohit KUMAR DCG; Jingoo Han
> Subject: Re: [PATCH v3 1/3] PCI: designware: Rename get_msi_data to
> get_msi_addr
> 
> [+cc Mohit, Jingoo]
> 
> On Tue, Sep 23, 2014 at 10:28:58PM +0800, Minghuan Lian wrote:
> > The function get_msi_data is used to return MSI message address.
> > In order to accurately express function purpose the patch rename it to
> > get_msi_addr.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> 
> I think this looks like a good idea, but it needs an ack from Mohit and/or
> Jingoo (cc'd).
> 

- Acked-by: Mohit KUMAR <mohit.kumar@st.com>

Thanks
Mohit

> You previously asked whether .get_msi_addr() should also be changed to
> return u64 instead of u32.  I think it should, and you can do that in a separate
> patch that also changes the use in dw_msi_setup_irq() to split the 64-bit
> result into msg.address_lo and msg.address_hi.
> 
> I don't see any implementations of .get_msi_data() or .get_msi_addr(), so
> this seems pretty straightforward.
> 
> Bjorn
> 
> > ---
> > Change log:
> > v3: no change
> > v2: no change just derived from v1
> >
> >  drivers/pci/host/pcie-designware.c | 4 ++--
> > drivers/pci/host/pcie-designware.h | 2 +-
> >  2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index 5d720c2..1c09f814 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip,
> struct pci_dev *pdev,
> >  	 */
> >  	desc->msi_attrib.multiple = msgvec;
> >
> > -	if (pp->ops->get_msi_data)
> > -		msg.address_lo = pp->ops->get_msi_data(pp);
> > +	if (pp->ops->get_msi_addr)
> > +		msg.address_lo = pp->ops->get_msi_addr(pp);
> >  	else
> >  		msg.address_lo = virt_to_phys((void *)pp->msi_data);
> >  	msg.address_hi = 0x0;
> > diff --git a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h
> > index 48f8670..904e40a 100644
> > --- a/drivers/pci/host/pcie-designware.h
> > +++ b/drivers/pci/host/pcie-designware.h
> > @@ -70,7 +70,7 @@ struct pcie_host_ops {
> >  	void (*host_init)(struct pcie_port *pp);
> >  	void (*msi_set_irq)(struct pcie_port *pp, int irq);
> >  	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
> > -	u32 (*get_msi_data)(struct pcie_port *pp);
> > +	u32 (*get_msi_addr)(struct pcie_port *pp);
> >  	void (*scan_bus)(struct pcie_port *pp);
> >  	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
> > };
> > --
> > 1.9.1
> >

RE: [PATCH] PCI: designware: Fix configuration base address

[Mohit KUMAR DCG]

Hello Minghuan,

> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Wednesday, September 24, 2014 4:23 AM
> To: Minghuan Lian
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Zang
> Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd
> Bergmann; Mohit KUMAR DCG; Jingoo Han
> Subject: Re: [PATCH] PCI: designware: Fix configuration base address
> 
> [+cc Mohit, Jingoo]
> 
> On Tue, Sep 23, 2014 at 10:28:56PM +0800, Minghuan Lian wrote:
> > The code has calculated cfg0_base and cfg1_base when parsing 'reg'
> > or 'ranges' property of PCI DTS node. so remove duplicate calculation.
> > And when using 'reg', resource cfg is not used, the removed code will
> > get incorrect configuration base.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> > ---
> >  drivers/pci/host/pcie-designware.c | 2 --
> >  1 file changed, 2 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index c28ca05..0f3cb2a 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >  	pp->mem_base = pp->mem.start;
> >
> >  	if (!pp->va_cfg0_base) {
> > -		pp->cfg0_base = pp->cfg.start;
> >  		pp->va_cfg0_base = devm_ioremap(pp->dev, pp-
> >cfg0_base,
> >  						pp->cfg0_size);
> >  		if (!pp->va_cfg0_base) {
> > @@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >  	}
> >
> >  	if (!pp->va_cfg1_base) {
> > -		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
> >  		pp->va_cfg1_base = devm_ioremap(pp->dev, pp-
> >cfg1_base,
> >  						pp->cfg1_size);
> >  		if (!pp->va_cfg1_base) {
> > --
> > 1.9.1
> >

- Acked-by: Mohit KUMAR <mohit.kumar@st.com>

Thanks
Mohit

RE: [PATCH] PCI: designware: Fix IO resource end address calculation

[Mohit KUMAR DCG]

> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Wednesday, September 24, 2014 4:24 AM
> To: Minghuan Lian
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Zang
> Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd
> Bergmann; Mohit KUMAR DCG; Jingoo Han
> Subject: Re: [PATCH] PCI: designware: Fix IO resource end address
> calculation
> 
> [+cc Mohit, Jingoo]
> 
> On Tue, Sep 23, 2014 at 10:28:57PM +0800, Minghuan Lian wrote:
> > End address should be equal to start_addr + size - 1.
> > The patch fixes PCI IO resource end address calculation.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> > ---
> >  drivers/pci/host/pcie-designware.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
> designware.c
> > index 0f3cb2a..c19184f7 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >  			pp->io.end = min_t(resource_size_t,
> >  					   IO_SPACE_LIMIT,
> >  					   range.pci_addr + range.size
> > -					   + global_io_offset);
> > +					   + global_io_offset - 1);
> >  			pp->io_size = resource_size(&pp->io);
> >  			pp->io_bus_addr = range.pci_addr;
> >  			pp->io_base = range.cpu_addr;
> > --
> > 1.9.1
> >
- Acked-by: Mohit KUMAR <mohit.kumar@st.com>

Thanks
Mohit

RE: [PATCH v3 2/3] PCI: designware: Add get_msi_data() to pcie_host_ops

[Mohit KUMAR DCG]

> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Wednesday, September 24, 2014 4:44 AM
> To: Minghuan Lian
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Zang
> Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd
> Bergmann; Mohit KUMAR DCG; Jingoo Han
> Subject: Re: [PATCH v3 2/3] PCI: designware: Add get_msi_data() to
> pcie_host_ops
> 
> [+cc Mohit, Jingoo]
> 
> On Tue, Sep 23, 2014 at 10:28:59PM +0800, Minghuan Lian wrote:
> > The patch adds get_msi_data() for some platforms to return their
> > special MSI message data.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> > ---
> > Change log:
> > v3: no change
> > v2: no change just derived from v1
> >
> >  drivers/pci/host/pcie-designware.c | 7 ++++++-
> > drivers/pci/host/pcie-designware.h | 1 +
> >  2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index 1c09f814..c28ca05 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -366,7 +366,12 @@ static int dw_msi_setup_irq(struct msi_chip *chip,
> struct pci_dev *pdev,
> >  	else
> >  		msg.address_lo = virt_to_phys((void *)pp->msi_data);
> >  	msg.address_hi = 0x0;
> > -	msg.data = pos;
> > +
> > +	if (pp->ops->get_msi_data)
> > +		msg.data = pp->ops->get_msi_data(pp, pos);
> > +	else
> > +		msg.data = pos;
> > +
> >  	write_msi_msg(irq, &msg);
> >
> >  	return 0;
> > diff --git a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h
> > index 904e40a..c625675 100644
> > --- a/drivers/pci/host/pcie-designware.h
> > +++ b/drivers/pci/host/pcie-designware.h
> > @@ -71,6 +71,7 @@ struct pcie_host_ops {
> >  	void (*msi_set_irq)(struct pcie_port *pp, int irq);
> >  	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
> >  	u32 (*get_msi_addr)(struct pcie_port *pp);
> > +	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
> >  	void (*scan_bus)(struct pcie_port *pp);
> >  	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
> > };
> > --
> > 1.9.1
> >
- Acked-by: Mohit KUMAR <mohit.kumar@st.com>

Thanks
Mohit

Re: [PATCH] PCI: designware: Fix configuration base address

[Bjorn Helgaas]

On Tue, Sep 23, 2014 at 10:28:56PM +0800, Minghuan Lian wrote:
> The code has calculated cfg0_base and cfg1_base when parsing 'reg'
> or 'ranges' property of PCI DTS node. so remove duplicate calculation.
> And when using 'reg', resource cfg is not used, the removed code
> will get incorrect configuration base.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

Applied to pci/host-designware with Mohit's ack for v3.18, thanks!

> ---
>  drivers/pci/host/pcie-designware.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index c28ca05..0f3cb2a 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  	pp->mem_base = pp->mem.start;
>  
>  	if (!pp->va_cfg0_base) {
> -		pp->cfg0_base = pp->cfg.start;
>  		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
>  						pp->cfg0_size);
>  		if (!pp->va_cfg0_base) {
> @@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  	}
>  
>  	if (!pp->va_cfg1_base) {
> -		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
>  		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
>  						pp->cfg1_size);
>  		if (!pp->va_cfg1_base) {
> -- 
> 1.9.1
> 

Re: [PATCH] PCI: designware: Fix IO resource end address calculation

[Bjorn Helgaas]

On Tue, Sep 23, 2014 at 10:28:57PM +0800, Minghuan Lian wrote:
> End address should be equal to start_addr + size - 1.
> The patch fixes PCI IO resource end address calculation.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

Applied to pci/host-designware with Mohit's ack for v3.18, thanks!

> ---
>  drivers/pci/host/pcie-designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 0f3cb2a..c19184f7 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  			pp->io.end = min_t(resource_size_t,
>  					   IO_SPACE_LIMIT,
>  					   range.pci_addr + range.size
> -					   + global_io_offset);
> +					   + global_io_offset - 1);
>  			pp->io_size = resource_size(&pp->io);
>  			pp->io_bus_addr = range.pci_addr;
>  			pp->io_base = range.cpu_addr;
> -- 
> 1.9.1
> 

Re: [PATCH v3 1/3] PCI: designware: Rename get_msi_data to get_msi_addr

[Bjorn Helgaas]

On Tue, Sep 23, 2014 at 10:28:58PM +0800, Minghuan Lian wrote:
> The function get_msi_data is used to return MSI message address.
> In order to accurately express function purpose the patch rename
> it to get_msi_addr.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

Applied patches 1 and 2 to pci/host-designware with Mohit's ack for v3.18,
thanks!

> ---
> Change log:
> v3: no change
> v2: no change just derived from v1
> 
>  drivers/pci/host/pcie-designware.c | 4 ++--
>  drivers/pci/host/pcie-designware.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 5d720c2..1c09f814 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
>  	 */
>  	desc->msi_attrib.multiple = msgvec;
>  
> -	if (pp->ops->get_msi_data)
> -		msg.address_lo = pp->ops->get_msi_data(pp);
> +	if (pp->ops->get_msi_addr)
> +		msg.address_lo = pp->ops->get_msi_addr(pp);
>  	else
>  		msg.address_lo = virt_to_phys((void *)pp->msi_data);
>  	msg.address_hi = 0x0;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index 48f8670..904e40a 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -70,7 +70,7 @@ struct pcie_host_ops {
>  	void (*host_init)(struct pcie_port *pp);
>  	void (*msi_set_irq)(struct pcie_port *pp, int irq);
>  	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
> -	u32 (*get_msi_data)(struct pcie_port *pp);
> +	u32 (*get_msi_addr)(struct pcie_port *pp);
>  	void (*scan_bus)(struct pcie_port *pp);
>  	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
>  };
> -- 
> 1.9.1
>