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From: Naveen Naidu <naveennaidu479@gmail.com>
To: bhelgaas@google.com
Cc: "Naveen Naidu" <naveennaidu479@gmail.com>,
	linux-kernel-mentees@lists.linuxfoundation.org,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Robert Richter" <rric@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-arm-kernel@lists.infradead.org (moderated list:PCIE DRIVER
	FOR CAVIUM THUNDERX)
Subject: [PATCH v2 05/24] PCI: thunder: Remove redundant error fabrication when device read fails
Date: Fri, 15 Oct 2021 20:08:46 +0530	[thread overview]
Message-ID: <2d825f341b95c2fd91aa749a3901f9c0912a2372.1634306198.git.naveennaidu479@gmail.com> (raw)
In-Reply-To: <cover.1634306198.git.naveennaidu479@gmail.com>

An MMIO read from a PCI device that doesn't exist or doesn't respond
causes a PCI error. There's no real data to return to satisfy the
CPU read, so most hardware fabricates ~0 data.

The host controller drivers sets the error response values (~0) and
returns an error when faulty hardware read occurs. But the error
response value (~0) is already being set in PCI_OP_READ and
PCI_USER_READ_CONFIG whenever a read by host controller driver fails.

Thus, it's no longer necessary for the host controller drivers to
fabricate any error response.

This helps unify PCI error response checking and make error check
consistent and easier to find.

Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
---
 drivers/pci/controller/pci-thunder-ecam.c | 46 ++++++++---------------
 drivers/pci/controller/pci-thunder-pem.c  |  4 +-
 2 files changed, 17 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/controller/pci-thunder-ecam.c b/drivers/pci/controller/pci-thunder-ecam.c
index ffd84656544f..a95bb58afd52 100644
--- a/drivers/pci/controller/pci-thunder-ecam.c
+++ b/drivers/pci/controller/pci-thunder-ecam.c
@@ -41,10 +41,9 @@ static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
 	}
 	if (where_a == 0x4) {
 		addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
-		if (!addr) {
-			*val = ~0;
+		if (!addr)
 			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
+
 		v = readl(addr);
 		v &= ~0xf;
 		v |= 2; /* EA entry-1. Base-L */
@@ -56,10 +55,9 @@ static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
 		u32 barl_rb;
 
 		addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
-		if (!addr) {
-			*val = ~0;
+		if (!addr)
 			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
+
 		barl_orig = readl(addr + 0);
 		writel(0xffffffff, addr + 0);
 		barl_rb = readl(addr + 0);
@@ -72,10 +70,9 @@ static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
 	}
 	if (where_a == 0xc) {
 		addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */
-		if (!addr) {
-			*val = ~0;
+		if (!addr)
 			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
+
 		v = readl(addr); /* EA entry-3. Base-H */
 		set_val(v, where, size, val);
 		return PCIBIOS_SUCCESSFUL;
@@ -104,10 +101,8 @@ static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn,
 	}
 
 	addr = bus->ops->map_bus(bus, devfn, where_a);
-	if (!addr) {
-		*val = ~0;
+	if (!addr)
 		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
 
 	v = readl(addr);
 
@@ -135,10 +130,8 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 	int where_a = where & ~3;
 
 	addr = bus->ops->map_bus(bus, devfn, 0xc);
-	if (!addr) {
-		*val = ~0;
+	if (!addr)
 		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
 
 	v = readl(addr);
 
@@ -146,10 +139,8 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 	cfg_type = (v >> 16) & 0x7f;
 
 	addr = bus->ops->map_bus(bus, devfn, 8);
-	if (!addr) {
-		*val = ~0;
+	if (!addr)
 		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
 
 	class_rev = readl(addr);
 	if (class_rev == 0xffffffff)
@@ -176,10 +167,8 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 	}
 
 	addr = bus->ops->map_bus(bus, devfn, 0);
-	if (!addr) {
-		*val = ~0;
+	if (!addr)
 		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
 
 	vendor_device = readl(addr);
 	if (vendor_device == 0xffffffff)
@@ -196,10 +185,9 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 		bool is_tns = (vendor_device == 0xa01f177d);
 
 		addr = bus->ops->map_bus(bus, devfn, 0x70);
-		if (!addr) {
-			*val = ~0;
+		if (!addr)
 			return PCIBIOS_DEVICE_NOT_FOUND;
-		}
+
 		/* E_CAP */
 		v = readl(addr);
 		has_msix = (v & 0xff00) != 0;
@@ -211,10 +199,9 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 		}
 		if (where_a == 0xb0) {
 			addr = bus->ops->map_bus(bus, devfn, where_a);
-			if (!addr) {
-				*val = ~0;
+			if (!addr)
 				return PCIBIOS_DEVICE_NOT_FOUND;
-			}
+
 			v = readl(addr);
 			if (v & 0xff00)
 				pr_err("Bad MSIX cap header: %08x\n", v);
@@ -268,10 +255,9 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 
 		if (where_a == 0x70) {
 			addr = bus->ops->map_bus(bus, devfn, where_a);
-			if (!addr) {
-				*val = ~0;
+			if (!addr)
 				return PCIBIOS_DEVICE_NOT_FOUND;
-			}
+
 			v = readl(addr);
 			if (v & 0xff00)
 				pr_err("Bad PCIe cap header: %08x\n", v);
diff --git a/drivers/pci/controller/pci-thunder-pem.c b/drivers/pci/controller/pci-thunder-pem.c
index 0660b9da204f..06a9855cb431 100644
--- a/drivers/pci/controller/pci-thunder-pem.c
+++ b/drivers/pci/controller/pci-thunder-pem.c
@@ -41,10 +41,8 @@ static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
 	struct pci_config_window *cfg = bus->sysdata;
 	struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
 
-	if (devfn != 0 || where >= 2048) {
-		*val = ~0;
+	if (devfn != 0 || where >= 2048)
 		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
 
 	/*
 	 * 32-bit accesses only.  Write the address to the low order
-- 
2.25.1


  parent reply	other threads:[~2021-10-15 14:42 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15 14:35 [PATCH v2 00/24] Unify PCI error response checking Naveen Naidu
2021-10-15 14:28 ` [PATCH v2 01/24] PCI: Add PCI_ERROR_RESPONSE and it's related definitions Naveen Naidu
2021-10-20 13:24   ` Rob Herring
2021-10-15 14:28 ` [PATCH v2 02/24] PCI: Set error response in config access defines when ops->read() fails Naveen Naidu
2021-10-20 13:41   ` Rob Herring
2021-10-20 13:52   ` Pali Rohár
2021-10-20 15:13     ` Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 03/24] PCI: Unify PCI error response checking Naveen Naidu
2021-10-20 13:13   ` Rob Herring
2021-10-20 15:15     ` Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 04/24] PCI: Remove redundant error fabrication when device read fails Naveen Naidu
2021-10-20 13:42   ` Rob Herring
2021-10-15 14:38 ` Naveen Naidu [this message]
2021-10-15 14:38 ` [PATCH v2 06/24] PCI: iproc: " Naveen Naidu
2021-10-15 16:49   ` Ray Jui
2021-10-15 17:05     ` Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 07/24] PCI: mediatek: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 08/24] PCI: exynos: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 09/24] PCI: histb: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 10/24] PCI: kirin: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 11/24] PCI: aardvark: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 12/24] PCI: mvebu: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 13/24] PCI: altera: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 14/24] PCI: rcar: " Naveen Naidu
2021-10-18 11:32   ` Geert Uytterhoeven
2021-10-18 11:51     ` Naveen Naidu
2021-10-18 12:00       ` Geert Uytterhoeven
2021-10-15 14:38 ` [PATCH v2 15/24] PCI: rockchip: " Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 16/24] PCI/ERR: Use RESPONSE_IS_PCI_ERROR() to check read from hardware Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 17/24] PCI: vmd: " Naveen Naidu
2021-10-15 14:52   ` Naveen Naidu
2021-10-15 14:38 ` [PATCH v2 18/24] PCI: pciehp: " Naveen Naidu
2021-10-15 15:15   ` Naveen Naidu
2021-10-15 14:39 ` [PATCH v2 19/24] PCI/DPC: " Naveen Naidu
2021-10-15 14:39 ` [PATCH v2 20/24] PCI/PME: " Naveen Naidu
2021-10-15 14:39 ` [PATCH v2 21/24] PCI: cpqphp: " Naveen Naidu
2021-10-15 14:39 ` [PATCH v2 22/24] PCI: keystone: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
2021-10-15 14:39 ` [PATCH v2 23/24] PCI: hv: Use PCI_ERROR_RESPONSE to specify hardware read error Naveen Naidu
2021-10-15 14:39 ` [PATCH v2 24/24] PCI: xgene: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu

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