RE: [PATCH V3 06/16] PCI: dwc: Add ext config space capability search API

[Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>]

On Wed, Apr 17, 2019 at 10:34:52, Vidya Sagar <vidyas@nvidia.com> wrote:

> On 4/17/2019 2:57 PM, Gustavo Pimentel wrote:
> > On Tue, Apr 16, 2019 at 20:27:20, Vidya Sagar <vidyas@nvidia.com> wrote:
> > 
> >> Add extended configuration space capability search API using struct dw_pcie *
> >> pointer
> >>
> >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> >> ---
> >> Changes from [v2]:
> >> * None
> >>
> >> Changes from [v1]:
> >> * This is a new patch in v2 series
> >>
> >>   drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
> >>   drivers/pci/controller/dwc/pcie-designware.h |  1 +
> >>   2 files changed, 42 insertions(+)
> >>
> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> >> index d68c123e409c..44c0ba078452 100644
> >> --- a/drivers/pci/controller/dwc/pcie-designware.c
> >> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> >> @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
> >>   	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
> >>   }
> >>   
> >> +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
> >> +					    int cap)
> >> +{
> >> +	u32 header;
> >> +	int ttl;
> >> +	int pos = PCI_CFG_SPACE_SIZE;
> >> +
> >> +	/* minimum 8 bytes per capability */
> >> +	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
> >> +
> >> +	if (start)
> >> +		pos = start;
> >> +
> >> +	header = dw_pcie_readl_dbi(pci, pos);
> >> +	/*
> >> +	 * If we have no capabilities, this is indicated by cap ID,
> >> +	 * cap version and next pointer all being 0.
> >> +	 */
> >> +	if (header == 0)
> >> +		return 0;
> >> +
> >> +	while (ttl-- > 0) {
> >> +		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
> >> +			return pos;
> >> +
> >> +		pos = PCI_EXT_CAP_NEXT(header);
> >> +		if (pos < PCI_CFG_SPACE_SIZE)
> >> +			break;
> >> +
> >> +		header = dw_pcie_readl_dbi(pci, pos);
> >> +	}
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
> >> +{
> >> +	return dw_pcie_find_next_ext_capability(pci, 0, cap);
> >> +}
> >> +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
> >> +
> >>   int dw_pcie_read(void __iomem *addr, int size, u32 *val)
> >>   {
> >>   	if (!IS_ALIGNED((uintptr_t)addr, size)) {
> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> >> index 4ccd4c706ddb..fa41d675c48f 100644
> >> --- a/drivers/pci/controller/dwc/pcie-designware.h
> >> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> >> @@ -248,6 +248,7 @@ struct dw_pcie {
> >>   		container_of((endpoint), struct dw_pcie, ep)
> >>   
> >>   u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
> >> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
> >>   
> >>   int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> >>   int dw_pcie_write(void __iomem *addr, int size, u32 val);
> >> -- 
> >> 2.17.1
> > 
> > This ext capability function is aimed to be used by the EP also?
> > 
> Yes. It can be used by EP also. Hence I added it in common files.


Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>