From: Stanimir Varbanov <svarbanov@mm-sol.com>
To: ansuelsmth@gmail.com, 'Bjorn Andersson' <bjorn.andersson@linaro.org>
Cc: 'Sham Muthayyan' <smuthayy@codeaurora.org>,
'Andy Gross' <agross@kernel.org>,
'Bjorn Helgaas' <bhelgaas@google.com>,
'Rob Herring' <robh+dt@kernel.org>,
'Mark Rutland' <mark.rutland@arm.com>,
'Lorenzo Pieralisi' <lorenzo.pieralisi@arm.com>,
'Andrew Murray' <amurray@thegoodpenguin.co.uk>,
'Philipp Zabel' <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: R: [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set tx term offset
Date: Wed, 13 May 2020 16:49:10 +0300 [thread overview]
Message-ID: <37ddf6ac-43c8-f2f1-ce53-e0959084b77c@mm-sol.com> (raw)
In-Reply-To: <02df01d62925$acd160a0$067421e0$@gmail.com>
On 5/13/20 3:54 PM, ansuelsmth@gmail.com wrote:
>> Hi Ansuel,
>>
>> On 5/1/20 1:06 AM, Ansuel Smith wrote:
>>> From: Sham Muthayyan <smuthayy@codeaurora.org>
>>>
>>> Add tx term offset support to pcie qcom driver need in some revision of
>>> the ipq806x SoC.
>>> Ipq8064 have tx term offset set to 7.
>>> Ipq8064-v2 revision and ipq8065 have the tx term offset set to 0.
>>>
>>> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
>>> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
>>> ---
>>> drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++
>>> 1 file changed, 15 insertions(+)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>> index da8058fd1925..372d2c8508b5 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>> @@ -45,6 +45,9 @@
>>> #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
>>>
>>> #define PCIE20_PARF_PHY_CTRL 0x40
>>> +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(12,
>> 16)
>>
>> The mask definition is not correct. Should be GENMASK(20, 16)
>>
>>> +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
>>> +
>>> #define PCIE20_PARF_PHY_REFCLK 0x4C
>>> #define PHY_REFCLK_SSP_EN BIT(16)
>>> #define PHY_REFCLK_USE_PAD BIT(12)
>>> @@ -118,6 +121,7 @@ struct qcom_pcie_resources_2_1_0 {
>>> u32 tx_swing_full;
>>> u32 tx_swing_low;
>>> u32 rx0_eq;
>>> + u8 phy_tx0_term_offset;
>>> };
>>>
>>> struct qcom_pcie_resources_1_0_0 {
>>> @@ -318,6 +322,11 @@ static int
>> qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
>>> if (IS_ERR(res->ext_reset))
>>> return PTR_ERR(res->ext_reset);
>>>
>>> + if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064"))
>>> + res->phy_tx0_term_offset = 7;
>>
>> Before your change the phy_tx0_term_offser was 0 for apq8064, but here
>> you change it to 7, why?
>>
>
> apq8064 board should use qcom,pcie-apq8064 right? This should be set to 0
> only with pcie-ipq8064 compatible. Tell me if I'm wrong.
Sorry, my fault. I read the compatible check above as apq8064 but it is ipq.
--
regards,
Stan
next prev parent reply other threads:[~2020-05-13 13:49 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 22:06 [PATCH v3 00/11] Multiple fixes in PCIe qcom driver Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-05-07 17:54 ` Rob Herring
2020-05-08 11:51 ` Stanimir Varbanov
2020-04-30 22:06 ` [PATCH v3 02/11] devicetree: bindings: pci: add missing clks to qcom,pcie Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 03/11] PCI: qcom: change duplicate PCI reset to phy reset Ansuel Smith
2020-05-07 17:57 ` Rob Herring
2020-04-30 22:06 ` [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x Ansuel Smith
2020-05-07 18:00 ` Rob Herring
2020-05-08 7:20 ` Philipp Zabel
2020-04-30 22:06 ` [PATCH v3 05/11] devicetree: bindings: pci: add ext reset to qcom,pcie Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 06/11] PCI: qcom: introduce qcom_clear_and_set_dword Ansuel Smith
2020-05-07 18:07 ` Rob Herring
2020-04-30 22:06 ` [PATCH v3 07/11] PCI: qcom: add support for defining some PARF params Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 08/11] devicetree: bindings: pci: document PARF params bindings Ansuel Smith
2020-05-07 18:10 ` Rob Herring
2020-05-07 19:34 ` R: " ansuelsmth
2020-05-12 15:45 ` Rob Herring
2020-05-13 11:43 ` Stanimir Varbanov
2020-05-13 12:56 ` R: " ansuelsmth
2020-05-20 10:01 ` Stanimir Varbanov
2020-04-30 22:06 ` [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set tx term offset Ansuel Smith
2020-05-07 18:13 ` Rob Herring
2020-05-08 22:00 ` R: " ansuelsmth
2020-05-13 11:37 ` Stanimir Varbanov
2020-05-13 12:54 ` R: " ansuelsmth
2020-05-13 13:49 ` Stanimir Varbanov [this message]
2020-04-30 22:06 ` [PATCH v3 10/11] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie Ansuel Smith
2020-05-07 18:14 ` Rob Herring
2020-04-30 22:06 ` [PATCH v3 11/11] PCI: qcom: add Force GEN1 support Ansuel Smith
2020-05-01 17:07 ` [PATCH v3 00/11] Multiple fixes in PCIe qcom driver Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=37ddf6ac-43c8-f2f1-ce53-e0959084b77c@mm-sol.com \
--to=svarbanov@mm-sol.com \
--cc=agross@kernel.org \
--cc=amurray@thegoodpenguin.co.uk \
--cc=ansuelsmth@gmail.com \
--cc=bhelgaas@google.com \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=smuthayy@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).