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From: Yicong Yang <yangyicong@huawei.com>
To: John Garry <john.garry@huawei.com>,
	Yicong Yang <yangyicong@hisilicon.com>,
	<gregkh@linuxfoundation.org>, <helgaas@kernel.org>,
	<alexander.shishkin@linux.intel.com>, <lorenzo.pieralisi@arm.com>,
	<will@kernel.org>, <mark.rutland@arm.com>,
	<mathieu.poirier@linaro.org>, <suzuki.poulose@arm.com>,
	<mike.leach@linaro.org>, <leo.yan@linaro.org>,
	<jonathan.cameron@huawei.com>, <daniel.thompson@linaro.org>,
	<joro@8bytes.org>, <shameerali.kolothum.thodi@huawei.com>,
	<robin.murphy@arm.com>, <peterz@infradead.org>,
	<mingo@redhat.com>, <acme@kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<coresight@lists.linaro.org>, <linux-pci@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<iommu@lists.linux-foundation.org>
Cc: <prime.zeng@huawei.com>, <liuqi115@huawei.com>,
	<zhangshaokun@hisilicon.com>, <linuxarm@huawei.com>,
	<song.bao.hua@hisilicon.com>
Subject: Re: [PATCH v4 3/8] hisi_ptt: Register PMU device for PTT trace
Date: Thu, 24 Feb 2022 12:04:24 +0800	[thread overview]
Message-ID: <6cc5392d-528f-8e43-1792-866be8b7d6f9@huawei.com> (raw)
In-Reply-To: <f5b245a3-6a17-af4b-4dfe-a59868cacbb0@huawei.com>

On 2022/2/22 19:17, John Garry wrote:
> 
>> +
>>   static irqreturn_t hisi_ptt_irq(int irq, void *context)
>>   {
>>       struct hisi_ptt *hisi_ptt = context;
>> @@ -169,7 +233,7 @@ static irqreturn_t hisi_ptt_irq(int irq, void *context)
>>       if (!(status & HISI_PTT_TRACE_INT_STAT_MASK))
>>           return IRQ_NONE;
>>   -    return IRQ_HANDLED;
>> +    return IRQ_WAKE_THREAD;
>>   }
>>     static void hisi_ptt_irq_free_vectors(void *pdev)
>> @@ -192,8 +256,10 @@ static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt)
>>       if (ret < 0)
>>           return ret;
>>   -    ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ),
>> -                   hisi_ptt_irq, 0, DRV_NAME, hisi_ptt);
>> +    ret = devm_request_threaded_irq(&pdev->dev,
> 
> why add code in patch 2/8 and then immediately change 3/8?
> 

My bad patch split. As replied to Patch 2, the whole IRQ handler part will be remove in Patch 2
and we won't have this changing here.

>> +                    pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ),
>> +                    hisi_ptt_irq, hisi_ptt_isr, 0,
>> +                    DRV_NAME, hisi_ptt);
>>       if (ret) {
>>           pci_err(pdev, "failed to request irq %d, ret = %d.\n",
>>               pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), ret);
>> @@ -270,6 +336,429 @@ static void hisi_ptt_init_ctrls(struct hisi_ptt *hisi_ptt)
>>       hisi_ptt->trace_ctrl.default_cpu = cpumask_first(cpumask_of_node(dev_to_node(&pdev->dev)));
>>   }
>>   +#define HISI_PTT_PMU_FILTER_IS_PORT    BIT(19)
>> +#define HISI_PTT_PMU_FILTER_VAL_MASK    GENMASK(15, 0)
>> +#define HISI_PTT_PMU_DIRECTION_MASK    GENMASK(23, 20)
>> +#define HISI_PTT_PMU_TYPE_MASK        GENMASK(31, 24)
>> +#define HISI_PTT_PMU_FORMAT_MASK    GENMASK(35, 32)
>> +
>> +static ssize_t available_root_port_filters_show(struct device *dev,
>> +                        struct device_attribute *attr,
>> +                        char *buf)
>> +{
>> +    struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev));
>> +    struct hisi_ptt_filter_desc *filter;
>> +    int pos = 0;
>> +
>> +    if (list_empty(&hisi_ptt->port_filters))
>> +        return sysfs_emit(buf, "\n");
>> +
>> +    mutex_lock(&hisi_ptt->mutex);
>> +    list_for_each_entry(filter, &hisi_ptt->port_filters, list)
>> +        pos += sysfs_emit_at(buf, pos, "%s    0x%05lx\n",
>> +                     pci_name(filter->pdev),
>> +                     hisi_ptt_get_filter_val(filter->pdev) |
>> +                     HISI_PTT_PMU_FILTER_IS_PORT);
>> +
>> +    mutex_unlock(&hisi_ptt->mutex);
>> +    return pos;
>> +}
>> +static DEVICE_ATTR_ADMIN_RO(available_root_port_filters);
>> +
>> +static ssize_t available_requester_filters_show(struct device *dev,
>> +                        struct device_attribute *attr,
>> +                        char *buf)
>> +{
>> +    struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev));
>> +    struct hisi_ptt_filter_desc *filter;
>> +    int pos = 0;
>> +
>> +    if (list_empty(&hisi_ptt->port_filters))
> 
> is this supposed to be req_filters? And is it safe to access without locking?
> 

Thanks for catching this! will fix it.

>> +        return sysfs_emit(buf, "\n");
>> +
>> +    mutex_lock(&hisi_ptt->mutex);
>> +    list_for_each_entry(filter, &hisi_ptt->req_filters, list)
>> +        pos += sysfs_emit_at(buf, pos, "%s    0x%05x\n",
>> +                     pci_name(filter->pdev),
>> +                     hisi_ptt_get_filter_val(filter->pdev));
>> +
>> +    mutex_unlock(&hisi_ptt->mutex);
>> +    return pos;
>> +}
>> +static DEVICE_ATTR_ADMIN_RO(available_requester_filters);
>> +
>> +PMU_FORMAT_ATTR(filter,        "config:0-19");
>> +PMU_FORMAT_ATTR(direction,    "config:20-23");
>> +PMU_FORMAT_ATTR(type,        "config:24-31");
>> +PMU_FORMAT_ATTR(format,        "config:32-35");
>> +
>> +static struct attribute *hisi_ptt_pmu_format_attrs[] = {
>> +    &format_attr_filter.attr,
>> +    &format_attr_direction.attr,
>> +    &format_attr_type.attr,
>> +    &format_attr_format.attr,
>> +    NULL
>> +};
>> +
>> +static struct attribute_group hisi_ptt_pmu_format_group = {
>> +    .name = "format",
>> +    .attrs = hisi_ptt_pmu_format_attrs,
>> +};
>> +
>> +static struct attribute *hisi_ptt_pmu_filter_attrs[] = {
>> +    &dev_attr_available_root_port_filters.attr,
>> +    &dev_attr_available_requester_filters.attr,
>> +    NULL
>> +};
>> +
>> +static struct attribute_group hisi_ptt_pmu_filter_group = {
>> +    .attrs = hisi_ptt_pmu_filter_attrs,
>> +};
>> +
>> +static const struct attribute_group *hisi_ptt_pmu_groups[] = {
>> +    &hisi_ptt_pmu_format_group,
>> +    &hisi_ptt_pmu_filter_group,
>> +    NULL
>> +};
>> +
>> +/*
>> + * The supported value of the direction parameter. See hisi_ptt.rst
>> + * documentation for more details.
>> + */
>> +static u32 hisi_ptt_trace_available_direction[] = {
>> +    0,
>> +    1,
>> +    2,
>> +    3,
> 
> this seems a very odd array.
> 

I copied part of the definition of this parameter from the hisi_ptt.rst below:

When the desired format is 4DW, directions and related values
supported are shown below:
4'b0000: inbound TLPs (P, NP, CPL)
4'b0001: outbound TLPs (P, NP, CPL)
4'b0010: outbound TLPs (P, NP, CPL) and inbound TLPs (P, NP, CPL B)
4'b0011: outbound TLPs (P, NP, CPL) and inbound TLPs (CPL A)
When the desired format is 8DW, directions and related values supported are
shown below:
4'b0000: reserved
4'b0001: outbound TLPs (P, NP, CPL)
4'b0010: inbound TLPs (P, NP, CPL B)
4'b0011: inbound TLPs (CPL A)

Since the meaning of the `direction` highly depends on the configuration of the `format`
so the meaning is not commented here but redirect the readers to the documentation
where have detailed description.

> And I assume it is const as it is modified - can this be non-global and tied to the device context?
> 

ok. will make const and into the functions which use this.

Thanks,
Yicong

>> +};
>> +
>> +/* Different types can be set simultaneously */
>> +static u32 hisi_ptt_trace_available_type[] = {
>> +    1,    /* posted_request */
>> +    2,    /* non-posted_request */
>> +    4,    /* completion */
>> +};
>> +
>> +static u32 hisi_ptt_trace_availble_format[] = {
>> +    0,    /* 4DW */
>> +    1,    /* 8DW */
>> +};
>> +
> .

  reply	other threads:[~2022-02-24  4:04 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-21  8:42 [PATCH v4 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang
2022-02-21  8:43 ` [PATCH v4 1/8] iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity Yicong Yang
2022-02-21  8:43 ` [PATCH v4 2/8] hwtracing: Add trace function support for HiSilicon PCIe Tune and Trace device Yicong Yang
2022-02-21 11:18   ` Jonathan Cameron
2022-02-21 13:13     ` Yicong Yang
2022-02-21 13:22       ` Jonathan Cameron
2022-02-22 11:06   ` John Garry
2022-02-24  3:53     ` Yicong Yang
2022-02-24 12:32       ` John Garry
2022-02-24 12:57         ` Yicong Yang
2022-02-21  8:43 ` [PATCH v4 3/8] hisi_ptt: Register PMU device for PTT trace Yicong Yang
2022-02-21 11:44   ` Jonathan Cameron
2022-02-21 13:26     ` Yicong Yang
2022-02-22  4:03       ` Yicong Yang
2022-02-22 11:17   ` John Garry
2022-02-24  4:04     ` Yicong Yang [this message]
2022-02-21  8:43 ` [PATCH v4 4/8] hisi_ptt: Add support for dynamically updating the filter list Yicong Yang
2022-02-21 11:51   ` Jonathan Cameron
2022-02-21  8:43 ` [PATCH v4 5/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device Yicong Yang
2022-02-21  8:43 ` [PATCH v4 6/8] perf tool: Add support for HiSilicon PCIe Tune and Trace device driver Yicong Yang
     [not found]   ` <58a37c21-cf22-4cce-9c45-51048594a941@gmail.com>
2022-02-23  2:36     ` Yicong Yang
2022-02-21  8:43 ` [PATCH v4 7/8] docs: Add HiSilicon PTT device driver documentation Yicong Yang
2022-02-21 11:59   ` Jonathan Cameron
2022-02-21  8:43 ` [PATCH v4 8/8] MAINTAINERS: Add maintainer for HiSilicon PTT driver Yicong Yang

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