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From: Baruch Siach <baruch@tkos.co.il>
To: Robert Marko <robert.marko@sartura.hr>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>,
	Kathiravan T <kathirav@codeaurora.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Bryan O'Donoghue <pure.logic@nexus-software.ie>,
	linux-pci@vger.kernel.org,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
Date: Tue, 15 Mar 2022 15:20:54 +0200	[thread overview]
Message-ID: <874k3zbaxc.fsf@tarshish> (raw)
In-Reply-To: <CA+HBbNEham1bukiEv5Px2=fCnqnbBKWBy3xOKe89fioQWttoGg@mail.gmail.com>

Hi Robert,

On Tue, Mar 15 2022, Robert Marko wrote:
> On Fri, Feb 11, 2022 at 5:06 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
>>
>> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
>> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
>> > ported from downstream Codeaurora v5.4 kernel. The main difference from
>> > downstream code is the split of PCIe registers configuration from .init to
>> > .post_init, since it requires phy_power_on().
>> >
>> > Tested on IPQ6010 based hardware.
[snip]
>> >
>> > Baruch Siach (2):
>> >   PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
>> >   PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
>> >
>> > Selvam Sathappan Periakaruppan (1):
>> >   PCI: qcom: Add IPQ60xx support
>> >
>> >  drivers/pci/controller/dwc/pcie-designware.h |   7 +
>> >  drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
>> >  drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
>> >  3 files changed, 160 insertions(+), 8 deletions(-)
>>
>> Bjorn, Andy,
>>
>> Can you ACK please if this series is ready to be merged ?
>
> This would also help the IPQ8074 which has the same controller for the
> Gen3 port.
>
> I have been using this for OpenWrt for a while and it works.

Thanks for your test report.

It would be nice to have a formal Tested-by for the pcie-qcom.c
patch. It might help to push the patch forward.

Can you also share the device-tree part? I'll add it to this series in
case it needs a respin.

Thanks,
baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

  reply	other threads:[~2022-03-15 13:36 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-07 14:51 [PATCH v6 0/3] PCI: IPQ6018 platform support Baruch Siach
2022-02-07 14:51 ` [PATCH v6 1/3] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
2022-02-07 14:51 ` [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Baruch Siach
2022-06-08 23:00   ` Pali Rohár
2022-06-09  3:27     ` Baruch Siach
2022-06-09  8:47       ` Pali Rohár
2022-02-07 14:51 ` [PATCH v6 3/3] PCI: qcom: Add IPQ60xx support Baruch Siach
2022-02-11 16:06 ` [PATCH v6 0/3] PCI: IPQ6018 platform support Lorenzo Pieralisi
2022-03-15 13:04   ` Robert Marko
2022-03-15 13:20     ` Baruch Siach [this message]
2022-03-15 13:41       ` Robert Marko
2022-04-12 16:12 ` Lorenzo Pieralisi
2022-05-11 14:03   ` Lorenzo Pieralisi
2022-06-07 13:12     ` Robert Marko
2022-06-08 20:24       ` Bjorn Helgaas
2022-06-09 13:10         ` Baruch Siach

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