Re: [PATCH v6 0/3] PCI: IPQ6018 platform support

From: Robert Marko <robert.marko@sartura.hr>
To: Baruch Siach <baruch@tkos.co.il>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>,
	Kathiravan T <kathirav@codeaurora.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	"Bryan O'Donoghue" <pure.logic@nexus-software.ie>,
	linux-pci@vger.kernel.org,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
Date: Tue, 15 Mar 2022 14:41:32 +0100	[thread overview]
Message-ID: <CA+HBbNEgQoNZ2v5Wr-KjJ3+U_NPzhW2Tz9bn7pTAUTQ-_owudw@mail.gmail.com> (raw)
In-Reply-To: <874k3zbaxc.fsf@tarshish>

On Tue, Mar 15, 2022 at 2:30 PM Baruch Siach <baruch@tkos.co.il> wrote:
>
> Hi Robert,
>
> On Tue, Mar 15 2022, Robert Marko wrote:
> > On Fri, Feb 11, 2022 at 5:06 PM Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com> wrote:
> >>
> >> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> >> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> >> > ported from downstream Codeaurora v5.4 kernel. The main difference from
> >> > downstream code is the split of PCIe registers configuration from .init to
> >> > .post_init, since it requires phy_power_on().
> >> >
> >> > Tested on IPQ6010 based hardware.
> [snip]
> >> >
> >> > Baruch Siach (2):
> >> >   PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> >> >   PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> >> >
> >> > Selvam Sathappan Periakaruppan (1):
> >> >   PCI: qcom: Add IPQ60xx support
> >> >
> >> >  drivers/pci/controller/dwc/pcie-designware.h |   7 +
> >> >  drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
> >> >  drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
> >> >  3 files changed, 160 insertions(+), 8 deletions(-)
> >>
> >> Bjorn, Andy,
> >>
> >> Can you ACK please if this series is ready to be merged ?
> >
> > This would also help the IPQ8074 which has the same controller for the
> > Gen3 port.
> >
> > I have been using this for OpenWrt for a while and it works.
>
> Thanks for your test report.
>
> It would be nice to have a formal Tested-by for the pcie-qcom.c
> patch. It might help to push the patch forward.

Hi Baruch, I am not sure whether a Tested-by would be applicable here as its
a different platform, that is why I left it out.
>
> Can you also share the device-tree part? I'll add it to this series in
> case it needs a respin.
Currently, the IPQ8074 DTS regarding QMP PCI PHY-s and PCI controllers is
incorrect, it was all based on v1 of the SoC which is not supported at all.
Gen3 QMP PHY support is currently missing for IPQ8074 and I am working on
upstreaming that and will fix up all of the PCI-related stuff in the
DTS after that.

So, I would prefer to keep those separate and let this series get
merged, especially
since the DTS part has already been merged.

Regards,
Robert
>
> Thanks,
> baruch
>
> --
>                                                      ~. .~   Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
>    - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr