Linux-PCI Archive on lore.kernel.org
 help / color / Atom feed
* [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
@ 2019-06-28  1:38 Xiaowei Bao
  2019-06-28  1:38 ` [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
  2019-08-12 10:12 ` [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Lorenzo Pieralisi
  0 siblings, 2 replies; 8+ messages in thread
From: Xiaowei Bao @ 2019-06-28  1:38 UTC (permalink / raw)
  To: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, kishon,
	lorenzo.pieralisi, arnd, gregkh, minghuan.Lian, mingkai.hu,
	roy.zang, kstewart, pombredanne, shawn.lin, linux-pci,
	devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
  Cc: Xiaowei Bao

The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
so set the bar_fixed_64bit with 0x14.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
 - Replace value 0x14 with a macro.
v3:
 - No change.

 drivers/pci/controller/dwc/pci-layerscape-ep.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index be61d96..227c33b 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
 	.linkup_notifier = false,
 	.msi_capable = true,
 	.msix_capable = false,
+	.bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
 };
 
 static const struct pci_epc_features*
-- 
1.7.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
  2019-06-28  1:38 [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Xiaowei Bao
@ 2019-06-28  1:38 ` Xiaowei Bao
  2019-08-12 10:06   ` Lorenzo Pieralisi
  2019-08-12 10:12 ` [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Lorenzo Pieralisi
  1 sibling, 1 reply; 8+ messages in thread
From: Xiaowei Bao @ 2019-06-28  1:38 UTC (permalink / raw)
  To: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, kishon,
	lorenzo.pieralisi, arnd, gregkh, minghuan.Lian, mingkai.hu,
	roy.zang, kstewart, pombredanne, shawn.lin, linux-pci,
	devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
  Cc: Xiaowei Bao

Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
 - No change.
v3:
 - modify the commit message.

 drivers/pci/controller/dwc/Kconfig  |   20 ++++++++++++++++++--
 drivers/pci/controller/dwc/Makefile |    3 ++-
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index a6ce1ee..a41ccf5 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -131,13 +131,29 @@ config PCI_KEYSTONE_EP
 	  DesignWare core functions to implement the driver.
 
 config PCI_LAYERSCAPE
-	bool "Freescale Layerscape PCIe controller"
+	bool "Freescale Layerscape PCIe controller - Host mode"
 	depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
 	depends on PCI_MSI_IRQ_DOMAIN
 	select MFD_SYSCON
 	select PCIE_DW_HOST
 	help
-	  Say Y here if you want PCIe controller support on Layerscape SoCs.
+	  Say Y here if you want to enable PCIe controller support on Layerscape
+	  SoCs to work in Host mode.
+	  This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
+	  determines which PCIe controller works in EP mode and which PCIe
+	  controller works in RC mode.
+
+config PCI_LAYERSCAPE_EP
+	bool "Freescale Layerscape PCIe controller - Endpoint mode"
+	depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
+	depends on PCI_ENDPOINT
+	select PCIE_DW_EP
+	help
+	  Say Y here if you want to enable PCIe controller support on Layerscape
+	  SoCs to work in Endpoint mode.
+	  This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
+	  determines which PCIe controller works in EP mode and which PCIe
+	  controller works in RC mode.
 
 config PCI_HISI
 	depends on OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index b085dfd..824fde7 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -8,7 +8,8 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
-obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
+obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
+obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
 obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
-- 
1.7.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
  2019-06-28  1:38 ` [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
@ 2019-08-12 10:06   ` Lorenzo Pieralisi
  2019-08-12 10:18     ` [EXT] " Xiaowei Bao
  0 siblings, 1 reply; 8+ messages in thread
From: Lorenzo Pieralisi @ 2019-08-12 10:06 UTC (permalink / raw)
  To: Xiaowei Bao
  Cc: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, kishon,
	arnd, gregkh, minghuan.Lian, mingkai.hu, roy.zang, kstewart,
	pombredanne, shawn.lin, linux-pci, devicetree, linux-kernel,
	linux-arm-kernel, linuxppc-dev

On Fri, Jun 28, 2019 at 09:38:26AM +0800, Xiaowei Bao wrote:
> Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
> v2:
>  - No change.
> v3:
>  - modify the commit message.
> 
>  drivers/pci/controller/dwc/Kconfig  |   20 ++++++++++++++++++--
>  drivers/pci/controller/dwc/Makefile |    3 ++-
>  2 files changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index a6ce1ee..a41ccf5 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -131,13 +131,29 @@ config PCI_KEYSTONE_EP
>  	  DesignWare core functions to implement the driver.
>  
>  config PCI_LAYERSCAPE
> -	bool "Freescale Layerscape PCIe controller"
> +	bool "Freescale Layerscape PCIe controller - Host mode"
>  	depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
>  	depends on PCI_MSI_IRQ_DOMAIN
>  	select MFD_SYSCON
>  	select PCIE_DW_HOST
>  	help
> -	  Say Y here if you want PCIe controller support on Layerscape SoCs.
> +	  Say Y here if you want to enable PCIe controller support on Layerscape
> +	  SoCs to work in Host mode.
> +	  This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]

What's "The RCW" ? This entry should explain why a kernel configuration
should enable it.

Lorenzo

> +	  determines which PCIe controller works in EP mode and which PCIe
> +	  controller works in RC mode.
> +
> +config PCI_LAYERSCAPE_EP
> +	bool "Freescale Layerscape PCIe controller - Endpoint mode"
> +	depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
> +	depends on PCI_ENDPOINT
> +	select PCIE_DW_EP
> +	help
> +	  Say Y here if you want to enable PCIe controller support on Layerscape
> +	  SoCs to work in Endpoint mode.
> +	  This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
> +	  determines which PCIe controller works in EP mode and which PCIe
> +	  controller works in RC mode.
>  
>  config PCI_HISI
>  	depends on OF && (ARM64 || COMPILE_TEST)
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index b085dfd..824fde7 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -8,7 +8,8 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
>  obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>  obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
>  obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
> +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> +obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
>  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
>  obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
>  obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> -- 
> 1.7.1
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
  2019-06-28  1:38 [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Xiaowei Bao
  2019-06-28  1:38 ` [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
@ 2019-08-12 10:12 ` Lorenzo Pieralisi
  2019-08-12 10:39   ` [EXT] " Xiaowei Bao
  1 sibling, 1 reply; 8+ messages in thread
From: Lorenzo Pieralisi @ 2019-08-12 10:12 UTC (permalink / raw)
  To: Xiaowei Bao, kishon
  Cc: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, arnd,
	gregkh, minghuan.Lian, mingkai.hu, roy.zang, kstewart,
	pombredanne, shawn.lin, linux-pci, devicetree, linux-kernel,
	linux-arm-kernel, linuxppc-dev

First off:

Trim the CC list, you CC'ed maintainers (and mailing lists) for no
reasons whatsover.

Then, read this:

https://lore.kernel.org/linux-pci/20171026223701.GA25649@bhelgaas-glaptop.roam.corp.google.com/

and make your patches compliant please.

On Fri, Jun 28, 2019 at 09:38:25AM +0800, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
> so set the bar_fixed_64bit with 0x14.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
> v2:
>  - Replace value 0x14 with a macro.
> v3:
>  - No change.
> 
>  drivers/pci/controller/dwc/pci-layerscape-ep.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index be61d96..227c33b 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
>  	.linkup_notifier = false,
>  	.msi_capable = true,
>  	.msix_capable = false,
> +	.bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),

I would appreciate Kishon's ACK on this.

Lorenzo

>  };
>  
>  static const struct pci_epc_features*
> -- 
> 1.7.1
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [EXT] Re: [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
  2019-08-12 10:06   ` Lorenzo Pieralisi
@ 2019-08-12 10:18     ` " Xiaowei Bao
  0 siblings, 0 replies; 8+ messages in thread
From: Xiaowei Bao @ 2019-08-12 10:18 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: bhelgaas, robh+dt, mark.rutland, shawnguo, Leo Li, kishon, arnd,
	gregkh, M.h. Lian, Mingkai Hu, Roy Zang, kstewart, pombredanne,
	shawn.lin, linux-pci, devicetree, linux-kernel, linux-arm-kernel,
	linuxppc-dev



> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019Äê8ÔÂ12ÈÕ 18:06
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com;
> arnd@arndb.de; gregkh@linuxfoundation.org; M.h. Lian
> <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang
> <roy.zang@nxp.com>; kstewart@linuxfoundation.org;
> pombredanne@nexb.com; shawn.lin@rock-chips.com;
> linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linuxppc-dev@lists.ozlabs.org
> Subject: [EXT] Re: [PATCHv3 2/2] PCI: layerscape: Add
> CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
> 
> Caution: EXT Email
> 
> On Fri, Jun 28, 2019 at 09:38:26AM +0800, Xiaowei Bao wrote:
> > Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> >  - No change.
> > v3:
> >  - modify the commit message.
> >
> >  drivers/pci/controller/dwc/Kconfig  |   20 ++++++++++++++++++--
> >  drivers/pci/controller/dwc/Makefile |    3 ++-
> >  2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/Kconfig
> > b/drivers/pci/controller/dwc/Kconfig
> > index a6ce1ee..a41ccf5 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -131,13 +131,29 @@ config PCI_KEYSTONE_EP
> >         DesignWare core functions to implement the driver.
> >
> >  config PCI_LAYERSCAPE
> > -     bool "Freescale Layerscape PCIe controller"
> > +     bool "Freescale Layerscape PCIe controller - Host mode"
> >       depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
> >       depends on PCI_MSI_IRQ_DOMAIN
> >       select MFD_SYSCON
> >       select PCIE_DW_HOST
> >       help
> > -       Say Y here if you want PCIe controller support on Layerscape SoCs.
> > +       Say Y here if you want to enable PCIe controller support on
> Layerscape
> > +       SoCs to work in Host mode.
> > +       This controller can work either as EP or RC. The
> > + RCW[HOST_AGT_PEX]
> 
> What's "The RCW" ? This entry should explain why a kernel configuration
> should enable it.
[Xiaowei Bao] Hi Lorenzo, the RCW full name is "reset configuration word", it can be built to a bin file and program to the flash, rather than configure by kernel, almost the NXP Layerscaple platform use this way.
> 
> Lorenzo
> 
> > +       determines which PCIe controller works in EP mode and which
> PCIe
> > +       controller works in RC mode.
> > +
> > +config PCI_LAYERSCAPE_EP
> > +     bool "Freescale Layerscape PCIe controller - Endpoint mode"
> > +     depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
> > +     depends on PCI_ENDPOINT
> > +     select PCIE_DW_EP
> > +     help
> > +       Say Y here if you want to enable PCIe controller support on
> Layerscape
> > +       SoCs to work in Endpoint mode.
> > +       This controller can work either as EP or RC. The
> RCW[HOST_AGT_PEX]
> > +       determines which PCIe controller works in EP mode and which
> PCIe
> > +       controller works in RC mode.
> >
> >  config PCI_HISI
> >       depends on OF && (ARM64 || COMPILE_TEST) diff --git
> > a/drivers/pci/controller/dwc/Makefile
> > b/drivers/pci/controller/dwc/Makefile
> > index b085dfd..824fde7 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -8,7 +8,8 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> >  obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> >  obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> >  obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> > -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
> >  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> >  obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> >  obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> > --
> > 1.7.1
> >

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
  2019-08-12 10:12 ` [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Lorenzo Pieralisi
@ 2019-08-12 10:39   ` " Xiaowei Bao
  2019-08-12 11:35     ` Lorenzo Pieralisi
  0 siblings, 1 reply; 8+ messages in thread
From: Xiaowei Bao @ 2019-08-12 10:39 UTC (permalink / raw)
  To: Lorenzo Pieralisi, kishon
  Cc: bhelgaas, robh+dt, mark.rutland, shawnguo, Leo Li, arnd, gregkh,
	M.h. Lian, Mingkai Hu, Roy Zang, kstewart, pombredanne,
	shawn.lin, linux-pci, devicetree, linux-kernel, linux-arm-kernel,
	linuxppc-dev



> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019Äê8ÔÂ12ÈÕ 18:12
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; kishon@ti.com
> Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; arnd@arndb.de;
> gregkh@linuxfoundation.org; M.h. Lian <minghuan.lian@nxp.com>; Mingkai
> Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> kstewart@linuxfoundation.org; pombredanne@nexb.com;
> shawn.lin@rock-chips.com; linux-pci@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
> Subject: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit
> property in EP driver.
> 
> Caution: EXT Email
> 
> First off:
> 
> Trim the CC list, you CC'ed maintainers (and mailing lists) for no reasons
> whatsover.
[Xiaowei Bao]Hi Lorenzo, I am not clear why the mail list is the CC, I use the command "git send-email --to", I will try to send the patch again, do I need to modify the version is v4 when I send this patch again?
> 
> Then, read this:
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Flinux-pci%2F20171026223701.GA25649%40bhelgaas-glaptop.roa
> m.corp.google.com%2F&amp;data=02%7C01%7Cxiaowei.bao%40nxp.com%7
> C1c586178e23c423a0e8808d71f0d8f6f%7C686ea1d3bc2b4c6fa92cd99c5c30
> 1635%7C0%7C0%7C637012015426788575&amp;sdata=3bx1bDFIzik8FnD0wl
> duAUv7wtLdD1J3hQ3xNH2xmFY%3D&amp;reserved=0
> 
> and make your patches compliant please.
> 
> On Fri, Jun 28, 2019 at 09:38:25AM +0800, Xiaowei Bao wrote:
> > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 is
> > 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, so set
> > the bar_fixed_64bit with 0x14.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> >  - Replace value 0x14 with a macro.
> > v3:
> >  - No change.
> >
> >  drivers/pci/controller/dwc/pci-layerscape-ep.c |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index be61d96..227c33b 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
> >       .linkup_notifier = false,
> >       .msi_capable = true,
> >       .msix_capable = false,
> > +     .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
> 
> I would appreciate Kishon's ACK on this.
> 
> Lorenzo
> 
> >  };
> >
> >  static const struct pci_epc_features*
> > --
> > 1.7.1
> >

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
  2019-08-12 10:39   ` [EXT] " Xiaowei Bao
@ 2019-08-12 11:35     ` Lorenzo Pieralisi
  2019-08-13  2:10       ` Xiaowei Bao
  0 siblings, 1 reply; 8+ messages in thread
From: Lorenzo Pieralisi @ 2019-08-12 11:35 UTC (permalink / raw)
  To: Xiaowei Bao
  Cc: kishon, bhelgaas, robh+dt, mark.rutland, shawnguo, Leo Li, arnd,
	gregkh, M.h. Lian, Mingkai Hu, Roy Zang, kstewart, pombredanne,
	shawn.lin, linux-pci, devicetree, linux-kernel, linux-arm-kernel,
	linuxppc-dev

On Mon, Aug 12, 2019 at 10:39:00AM +0000, Xiaowei Bao wrote:
> 
> 
> > -----Original Message-----
> > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Sent: 2019年8月12日 18:12
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>; kishon@ti.com
> > Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; arnd@arndb.de;
> > gregkh@linuxfoundation.org; M.h. Lian <minghuan.lian@nxp.com>; Mingkai
> > Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> > kstewart@linuxfoundation.org; pombredanne@nexb.com;
> > shawn.lin@rock-chips.com; linux-pci@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
> > Subject: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit
> > property in EP driver.
> > 
> > Caution: EXT Email
> > 
> > First off:
> > 
> > Trim the CC list, you CC'ed maintainers (and mailing lists) for no reasons
> > whatsover.
> [Xiaowei Bao]Hi Lorenzo, I am not clear why the mail list is the CC, I use the command "git send-email --to", I will try to send the patch again, do I need to modify the version is v4 when I send this patch again?

Yes you do.

Wrap lines to max 80 characters. There is no need to add [Xiaowei Bao].

1) Read, email etiquette

https://kernelnewbies.org/PatchCulture

2) get_maintainer.pl -f drivers/pci/controller/dwc/pci-layerscape.c

Compare the output to the people in CC, trim it accordingly.

3) The NXP maintainers in the MAINTAINERS file have not given a single
   comment for this patchset. Either they show up or I will remove them
   from the MAINTAINERS list.

4) Before submitting patches, talk to someone at NXP who can help you
   format them in preparation for posting, I do not have time to write
   guidelines for everyone posting on linux-pci, sorry, the information
   is out there if you care to read it.

Thanks,
Lorenzo

> > 
> > Then, read this:
> > 
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> > rnel.org%2Flinux-pci%2F20171026223701.GA25649%40bhelgaas-glaptop.roa
> > m.corp.google.com%2F&amp;data=02%7C01%7Cxiaowei.bao%40nxp.com%7
> > C1c586178e23c423a0e8808d71f0d8f6f%7C686ea1d3bc2b4c6fa92cd99c5c30
> > 1635%7C0%7C0%7C637012015426788575&amp;sdata=3bx1bDFIzik8FnD0wl
> > duAUv7wtLdD1J3hQ3xNH2xmFY%3D&amp;reserved=0
> > 
> > and make your patches compliant please.
> > 
> > On Fri, Jun 28, 2019 at 09:38:25AM +0800, Xiaowei Bao wrote:
> > > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 is
> > > 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, so set
> > > the bar_fixed_64bit with 0x14.
> > >
> > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > ---
> > > v2:
> > >  - Replace value 0x14 with a macro.
> > > v3:
> > >  - No change.
> > >
> > >  drivers/pci/controller/dwc/pci-layerscape-ep.c |    1 +
> > >  1 files changed, 1 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > index be61d96..227c33b 100644
> > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
> > >       .linkup_notifier = false,
> > >       .msi_capable = true,
> > >       .msix_capable = false,
> > > +     .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
> > 
> > I would appreciate Kishon's ACK on this.
> > 
> > Lorenzo
> > 
> > >  };
> > >
> > >  static const struct pci_epc_features*
> > > --
> > > 1.7.1
> > >

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
  2019-08-12 11:35     ` Lorenzo Pieralisi
@ 2019-08-13  2:10       ` Xiaowei Bao
  0 siblings, 0 replies; 8+ messages in thread
From: Xiaowei Bao @ 2019-08-13  2:10 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: kishon, bhelgaas, robh+dt, mark.rutland, shawnguo, Leo Li, arnd,
	gregkh, M.h. Lian, Mingkai Hu, Roy Zang, kstewart, pombredanne,
	shawn.lin, linux-pci, devicetree, linux-kernel, linux-arm-kernel,
	linuxppc-dev



> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年8月12日 19:36
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: kishon@ti.com; bhelgaas@google.com; robh+dt@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; arnd@arndb.de; gregkh@linuxfoundation.org; M.h.
> Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy
> Zang <roy.zang@nxp.com>; kstewart@linuxfoundation.org;
> pombredanne@nexb.com; shawn.lin@rock-chips.com;
> linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linuxppc-dev@lists.ozlabs.org
> Subject: Re: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit
> property in EP driver.
> 
> Caution: EXT Email
> 
> On Mon, Aug 12, 2019 at 10:39:00AM +0000, Xiaowei Bao wrote:
> >
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > Sent: 2019年8月12日 18:12
> > > To: Xiaowei Bao <xiaowei.bao@nxp.com>; kishon@ti.com
> > > Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; arnd@arndb.de;
> > > gregkh@linuxfoundation.org; M.h. Lian <minghuan.lian@nxp.com>;
> > > Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> > > kstewart@linuxfoundation.org; pombredanne@nexb.com;
> > > shawn.lin@rock-chips.com; linux-pci@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
> > > Subject: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the
> > > bar_fixed_64bit property in EP driver.
> > >
> > > Caution: EXT Email
> > >
> > > First off:
> > >
> > > Trim the CC list, you CC'ed maintainers (and mailing lists) for no
> > > reasons whatsover.
> > [Xiaowei Bao]Hi Lorenzo, I am not clear why the mail list is the CC, I use the
> command "git send-email --to", I will try to send the patch again, do I need to
> modify the version is v4 when I send this patch again?
> 
> Yes you do.
> 
> Wrap lines to max 80 characters. There is no need to add [Xiaowei Bao].
OK, thanks a lot.
> 
> 1) Read, email etiquette
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fkernel
> newbies.org%2FPatchCulture&amp;data=02%7C01%7Cxiaowei.bao%40nxp.c
> om%7C73a3b6160aad401b72d208d71f193ae1%7C686ea1d3bc2b4c6fa92cd
> 99c5c301635%7C0%7C0%7C637012065548351226&amp;sdata=y6xa5nMkB
> qkWz7SBFdc%2F0lcQvzI%2F9HjEyC5%2Bk0RxczI%3D&amp;reserved=0
> 
> 2) get_maintainer.pl -f drivers/pci/controller/dwc/pci-layerscape.c
> 
> Compare the output to the people in CC, trim it accordingly.
> 
> 3) The NXP maintainers in the MAINTAINERS file have not given a single
>    comment for this patchset. Either they show up or I will remove them
>    from the MAINTAINERS list.
> 
> 4) Before submitting patches, talk to someone at NXP who can help you
>    format them in preparation for posting, I do not have time to write
>    guidelines for everyone posting on linux-pci, sorry, the information
>    is out there if you care to read it.
> 
> Thanks,
> Lorenzo
> 
> > >
> > > Then, read this:
> > >
> > > https://lore.ke
> > >
> rnel.org%2Flinux-pci%2F20171026223701.GA25649%40bhelgaas-glaptop.roa
> > >
> m.corp.google.com%2F&amp;data=02%7C01%7Cxiaowei.bao%40nxp.com%7
> > >
> C1c586178e23c423a0e8808d71f0d8f6f%7C686ea1d3bc2b4c6fa92cd99c5c30
> > >
> 1635%7C0%7C0%7C637012015426788575&amp;sdata=3bx1bDFIzik8FnD0wl
> > > duAUv7wtLdD1J3hQ3xNH2xmFY%3D&amp;reserved=0
> > >
> > > and make your patches compliant please.
> > >
> > > On Fri, Jun 28, 2019 at 09:38:25AM +0800, Xiaowei Bao wrote:
> > > > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> > > > is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
> > > > so set the bar_fixed_64bit with 0x14.
> > > >
> > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > ---
> > > > v2:
> > > >  - Replace value 0x14 with a macro.
> > > > v3:
> > > >  - No change.
> > > >
> > > >  drivers/pci/controller/dwc/pci-layerscape-ep.c |    1 +
> > > >  1 files changed, 1 insertions(+), 0 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > index be61d96..227c33b 100644
> > > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie
> *pci)
> > > >       .linkup_notifier = false,
> > > >       .msi_capable = true,
> > > >       .msix_capable = false,
> > > > +     .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
> > >
> > > I would appreciate Kishon's ACK on this.
> > >
> > > Lorenzo
> > >
> > > >  };
> > > >
> > > >  static const struct pci_epc_features*
> > > > --
> > > > 1.7.1
> > > >

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, back to index

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-28  1:38 [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Xiaowei Bao
2019-06-28  1:38 ` [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
2019-08-12 10:06   ` Lorenzo Pieralisi
2019-08-12 10:18     ` [EXT] " Xiaowei Bao
2019-08-12 10:12 ` [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Lorenzo Pieralisi
2019-08-12 10:39   ` [EXT] " Xiaowei Bao
2019-08-12 11:35     ` Lorenzo Pieralisi
2019-08-13  2:10       ` Xiaowei Bao

Linux-PCI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
		linux-pci@vger.kernel.org linux-pci@archiver.kernel.org
	public-inbox-index linux-pci


Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci


AGPL code for this site: git clone https://public-inbox.org/ public-inbox