From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"arnd@arndb.de" <arnd@arndb.de>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes
Date: Mon, 3 Jun 2019 12:49:55 +0000 [thread overview]
Message-ID: <AM6PR04MB578147FD591EB0059646023D84140@AM6PR04MB5781.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <CAKnKUHH8JU2Bqgq90rfgZ8r0xxB_RMRj16DBBLDhMpg3mwFU2Q@mail.gmail.com>
Hi Karthikeyan,
Thanks a lot for your comments!
> -----Original Message-----
> From: Karthikeyan Mitran [mailto:m.karthikeyan@mobiveil.co.in]
> Sent: 2019年6月3日 13:13
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; arnd@arndb.de;
> mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> lorenzo.pieralisi@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes
>
> Hi Hou Zhiqiang
> Two instances [@3600000 and @3800000] of the six has a different
> window count, the RC can not have more than 8 windows.
> apio-wins = <256>; //Can we change it to 8
> ppio-wins = <24>; //Can we change it to 8
>
I checked with hardware team, the PCIe controllers @3600000 and @3800000 support
up to x8 and SRIOV, these 2 controllers have different number of inbound and outbound
windows from the other 4 PCIe controllers which are support up to x4 and not support
SRIOV.
> On Tue, May 28, 2019 at 12:20 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The LX2160A integrated 6 PCIe Gen4 controllers.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V6:
> > - No change.
> >
> > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163
> > ++++++++++++++++++
> > 1 file changed, 163 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index 125a8cc2c5b3..7a2b91ff1fbc 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -964,5 +964,168 @@
> > };
> > };
> > };
> > +
> > + pcie@3400000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000
> /* controller registers */
> > + 0x80 0x00000000 0x0 0x00001000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = <GIC_SPI 108
> IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 108
> IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 108
> IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <8>;
> > + ppio-wins = <8>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x82000000 0x0 0x40000000 0x80
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI
> 109 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0
> GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0
> GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0
> GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@3500000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03500000 0x0 0x00100000
> /* controller registers */
> > + 0x88 0x00000000 0x0 0x00001000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = <GIC_SPI 113
> IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 113
> IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 113
> IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <8>;
> > + ppio-wins = <8>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x82000000 0x0 0x40000000 0x88
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI
> 114 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0
> GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0
> GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0
> GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@3600000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03600000 0x0 0x00100000
> /* controller registers */
> > + 0x90 0x00000000 0x0 0x00001000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <256>;
> > + ppio-wins = <24>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x82000000 0x0 0x40000000 0x90
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI
> 119 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0
> GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0
> GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0
> GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@3700000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03700000 0x0 0x00100000
> /* controller registers */
> > + 0x98 0x00000000 0x0 0x00001000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = <GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <8>;
> > + ppio-wins = <8>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x82000000 0x0 0x40000000 0x98
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI
> 124 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0
> GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0
> GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0
> GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@3800000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03800000 0x0 0x00100000
> /* controller registers */
> > + 0xa0 0x00000000 0x0 0x00001000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = <GIC_SPI 128
> IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 128
> IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 128
> IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <256>;
> > + ppio-wins = <24>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x82000000 0x0 0x40000000 0xa0
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI
> 129 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0
> GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0
> GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0
> GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@3900000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03900000 0x0 0x00100000
> /* controller registers */
> > + 0xa8 0x00000000 0x0 0x00001000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = <GIC_SPI 103
> IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 103
> IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 103
> IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <8>;
> > + ppio-wins = <8>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x82000000 0x0 0x40000000 0xa8
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI
> 104 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0
> GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0
> GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0
> GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > };
> > };
> > --
> > 2.17.1
> >
>
>
> --
> Thanks,
> Regards,
> Karthikeyan Mitran
>
> --
> Mobiveil INC., CONFIDENTIALITY NOTICE: This e-mail message, including any
> attachments, is for the sole use of the intended recipient(s) and may contain
> proprietary confidential or privileged information or otherwise be protected
> by law. Any unauthorized review, use, disclosure or distribution is prohibited. If
> you are not the intended recipient, please notify the sender and destroy all
> copies and the original message.
Thanks,
Zhiqiang
next prev parent reply other threads:[~2019-06-03 12:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 6:49 [PATCHv6 0/6] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-05-28 6:50 ` [PATCHv6 1/6] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-05-28 6:50 ` [PATCHv6 2/6] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host Z.q. Hou
2019-05-28 6:50 ` [PATCHv6 3/6] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-05-28 6:50 ` [PATCHv6 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-05-28 6:50 ` [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes Z.q. Hou
2019-06-03 5:12 ` Karthikeyan Mitran
2019-06-03 12:49 ` Z.q. Hou [this message]
2019-05-28 6:50 ` [PATCHv6 6/6] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 Z.q. Hou
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