From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Johan Hovold <johan@kernel.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stephen Boyd" <swboyd@chromium.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Taniya Das" <quic_tdas@quicinc.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Johan Hovold" <johan+linaro@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v7 3/6] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
Date: Fri, 20 May 2022 19:54:08 +0300 [thread overview]
Message-ID: <CAA8EJpoFe=37G7dxecDqP922bMuktXyPmpY3rWp2Yr6J2hT4zA@mail.gmail.com> (raw)
In-Reply-To: <Yoe9VSxzOs733LTz@hovoldconsulting.com>
On Fri, 20 May 2022 at 19:09, Johan Hovold <johan@kernel.org> wrote:
>
> On Fri, May 20, 2022 at 04:58:41AM +0300, Dmitry Baryshkov wrote:
> > Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
> > the clock framework automatically park the clock when the clock is
> > switched off and restore the parent when the clock is switched on.
> >
> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> For the benefit of others using the new phy_mux implementation, it would
> have been better to just do a revert of the safe-mux change. Would make
> reviewing easier too.
Fine with me, I hesitated between these two variants and settled on
having a smaller amount of noise. I'll change this in next iteration.
>
> > ---
> > drivers/clk/qcom/gcc-sm8450.c | 72 +++++++++++------------------------
> > 1 file changed, 22 insertions(+), 50 deletions(-)
>
> > -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> > - .reg = 0x7b060,
> > - .shift = 0,
> > - .width = 2,
> > - .safe_src_parent = P_BI_TCXO,
> > - .parent_map = gcc_parent_map_4,
> > - .clkr = {
> > - .hw.init = &(struct clk_init_data){
> > - .name = "gcc_pcie_0_pipe_clk_src",
> > - .parent_data = gcc_parent_data_4,
> > - .num_parents = ARRAY_SIZE(gcc_parent_data_4),
> > - .ops = &clk_regmap_mux_safe_ops,
> > +static struct clk_regmap gcc_pcie_0_pipe_clk_src = {
> > + .enable_reg = 0x7b060,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gcc_pcie_0_pipe_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "pcie_0_pipe_clk",
> > },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + .ops = &clk_regmap_phy_mux_ops,
> > },
> > };
>
> And again, this would be easier to understand with a dedicated struct
> clk_regmap_phy_mux (whose definition you can look up and find a
> description of how it is intended to be use).
Or one can lookup the definition of clk_regmap_phy_mux_ops and read
the corresponding text. But I see your point, let's bring it back.
--
With best wishes
Dmitry
next prev parent reply other threads:[~2022-05-20 16:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-20 1:58 [PATCH v7 0/6] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Dmitry Baryshkov
2022-05-20 1:58 ` [PATCH v7 1/6] PCI: qcom: Remove unnecessary pipe_clk handling Dmitry Baryshkov
2022-05-20 1:58 ` [PATCH v7 2/6] clk: qcom: regmap: add PHY clock source implementation Dmitry Baryshkov
2022-05-20 16:04 ` Johan Hovold
2022-05-20 1:58 ` [PATCH v7 3/6] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks Dmitry Baryshkov
2022-05-20 16:09 ` Johan Hovold
2022-05-20 16:54 ` Dmitry Baryshkov [this message]
2022-05-20 1:58 ` [PATCH v7 4/6] clk: qcom: gcc-sc7280: " Dmitry Baryshkov
2022-05-20 1:58 ` [PATCH v7 5/6] Revert "clk: qcom: regmap-mux: add pipe clk implementation" Dmitry Baryshkov
2022-05-20 16:11 ` Johan Hovold
2022-05-20 1:58 ` [PATCH v7 6/6] PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov
2022-05-20 16:13 ` Johan Hovold
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