Re: [PATCH v7 3/6] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks

[Johan Hovold <johan@kernel.org>]

On Fri, May 20, 2022 at 04:58:41AM +0300, Dmitry Baryshkov wrote:
> Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
> the clock framework automatically park the clock when the clock is
> switched off and restore the parent when the clock is switched on.
> 
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

For the benefit of others using the new phy_mux implementation, it would
have been better to just do a revert of the safe-mux change. Would make
reviewing easier too.

> ---
>  drivers/clk/qcom/gcc-sm8450.c | 72 +++++++++++------------------------
>  1 file changed, 22 insertions(+), 50 deletions(-)
 
> -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> -	.reg = 0x7b060,
> -	.shift = 0,
> -	.width = 2,
> -	.safe_src_parent = P_BI_TCXO,
> -	.parent_map = gcc_parent_map_4,
> -	.clkr = {
> -		.hw.init = &(struct clk_init_data){
> -			.name = "gcc_pcie_0_pipe_clk_src",
> -			.parent_data = gcc_parent_data_4,
> -			.num_parents = ARRAY_SIZE(gcc_parent_data_4),
> -			.ops = &clk_regmap_mux_safe_ops,
> +static struct clk_regmap gcc_pcie_0_pipe_clk_src = {
> +	.enable_reg = 0x7b060,
> +	.hw.init = &(struct clk_init_data){
> +		.name = "gcc_pcie_0_pipe_clk_src",
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pcie_0_pipe_clk",
>  		},
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_regmap_phy_mux_ops,
>  	},
>  };

And again, this would be easier to understand with a dedicated struct
clk_regmap_phy_mux (whose definition you can look up and find a
description of how it is intended to be use).

Johan