From: Christian Gmeiner <christian.gmeiner@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Kishon Vijay Abraham I" <kishon@ti.com>,
LKML <linux-kernel@vger.kernel.org>,
"Tom Joseph" <tjoseph@cadence.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: cadence: respond to received PTM Requests
Date: Fri, 18 Feb 2022 14:42:24 +0100 [thread overview]
Message-ID: <CAH9NwWc_c=Cow9_9qp27Q7gtXFdCekQuEHUx+E9g5HivS82MAw@mail.gmail.com> (raw)
In-Reply-To: <20220218132037.GA345784@bhelgaas>
Hi Bjorn,
Am Fr., 18. Feb. 2022 um 14:20 Uhr schrieb Bjorn Helgaas <helgaas@kernel.org>:
>
> On Fri, Feb 18, 2022 at 04:26:48PM +0530, Kishon Vijay Abraham I wrote:
> > Hi Bjorn,
> >
> > On 01/02/22 3:35 am, Bjorn Helgaas wrote:
> > > Update subject line to match previous conventions ("git log --oneline
> > > drivers/pci/controller/cadence/pcie-cadence-host.c" to see).
> > >
> > > On Mon, Jan 31, 2022 at 01:08:27PM +0100, Christian Gmeiner wrote:
> > >> This enables the Controller [RP] to automatically respond
> > >> with Response/ResponseD messages.
> > >
>
> > >> +static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
> > >> +{
> > >> + u32 val;
> > >> +
> > >> + val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
> > >> + cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
> > >
> > > I assume this is some device-specific enable bit that is effectively
> > > ANDed with PCI_PTM_CTRL_ENABLE in the Precision Time Measurement
> > > Capability?
> >
> > That's correct. This bit enables Controller [RP] to respond to the
> > received PTM Requests.
>
> Great! Christian, can you update the commit log to reflect that
> both this bit *and* PCI_PTM_CTRL_ENABLE must be set for the RP to
> respond to received PTM Requests?
>
Would something like this work for you?
---8<---
PCI: cadence: Enable Controller to respond to received PTM Requests
This enables the Controller [RP] to automatically respond with
Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
and PCI_PTM_CTRL_ENABLE bits are both set.
---8<---
> When CDNS_PCIE_LM_TPM_CTRL_PTMRSEN is cleared, do PCI_PTM_CAP_ROOT
> and the PTM Responder Capable bit (for which we don't have a #define)
> read as zero?
>
I can test this out if needed for this change.. but that won't happen
before Monday.
> I think that would be the correct behavior per PCIe r6.0, sec
> 7.9.15.2, and it would avoid the confusion of having the PTM
> Capability register advertise functionality that cannot be enabled via
> the PTM Control register.
>
> > >> +/* PTM Control Register */
> > >> +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8)
>
> Other #defines in this file use lower-case hex.
I changed this in V2.
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
next prev parent reply other threads:[~2022-02-18 13:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-31 12:08 [PATCH] PCI: cadence: respond to received PTM Requests Christian Gmeiner
2022-01-31 22:05 ` Bjorn Helgaas
2022-02-04 14:45 ` Christian Gmeiner
2022-02-18 10:56 ` Kishon Vijay Abraham I
2022-02-18 13:13 ` Christian Gmeiner
2022-02-18 13:20 ` Bjorn Helgaas
2022-02-18 13:42 ` Christian Gmeiner [this message]
2022-02-22 14:10 ` Kishon Vijay Abraham I
2022-04-29 10:56 ` Lorenzo Pieralisi
2022-04-29 19:28 ` Bjorn Helgaas
2022-05-05 14:43 ` Dominic Rath
2022-05-05 14:48 ` Christian Gmeiner
2022-05-11 12:37 ` Lorenzo Pieralisi
2022-05-12 6:00 ` Christian Gmeiner
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