* [PATCH 0/2] PCI: cadence: Set LTSSM Detect.Quiet state delay. @ 2021-03-09 7:31 Nadeem Athani 2021-03-09 7:31 ` [PATCH 1/2] dt-bindings:pci: " Nadeem Athani 2021-03-09 7:31 ` [PATCH 2/2] PCI: cadence: " Nadeem Athani 0 siblings, 2 replies; 7+ messages in thread From: Nadeem Athani @ 2021-03-09 7:31 UTC (permalink / raw) To: tjoseph, bhelgaas, robh+dt, linux-pci, devicetree, linux-kernel, lorenzo.pieralisi, robh, kishon Cc: mparab, sjakhade, nadeem, pthombar This patch includes a set of two patches. First patch for adding a new property detect-quiet-min-delay in yaml file. Second patch programs the delay value in host pcie driver. The parameter detect-quiet-min-delay can be used to program the minimum time that LTSSM waits on entering Detect.Quiet state. 00 : 0us minimum wait time in Detect.Quiet state. 01 : 100us minimum wait time in Detect.Quiet state. 10 : 1000us minimum wait time in Detect.Quiet state. 11 : 2000us minimum wait time in Detect.Quiet state. Nadeem Athani (2): dt-bindings:pci: Set LTSSM Detect.Quiet state delay. PCI: cadence: Set LTSSM Detect.Quiet state delay. .../bindings/pci/cdns,cdns-pcie-host.yaml | 13 +++++++++++++ drivers/pci/controller/cadence/pcie-cadence-host.c | 22 ++++++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 10 ++++++++++ 3 files changed, 45 insertions(+) -- 2.15.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] dt-bindings:pci: Set LTSSM Detect.Quiet state delay. 2021-03-09 7:31 [PATCH 0/2] PCI: cadence: Set LTSSM Detect.Quiet state delay Nadeem Athani @ 2021-03-09 7:31 ` Nadeem Athani 2021-03-09 16:46 ` Rob Herring 2021-03-09 17:19 ` Rob Herring 2021-03-09 7:31 ` [PATCH 2/2] PCI: cadence: " Nadeem Athani 1 sibling, 2 replies; 7+ messages in thread From: Nadeem Athani @ 2021-03-09 7:31 UTC (permalink / raw) To: tjoseph, bhelgaas, robh+dt, linux-pci, devicetree, linux-kernel, lorenzo.pieralisi, robh, kishon Cc: mparab, sjakhade, nadeem, pthombar The parameter detect-quiet-min-delay can be used to program the minimum time that LTSSM waits on entering Detect.Quiet state. 00 : 0us minimum wait time in Detect.Quiet state. 01 : 100us minimum wait time in Detect.Quiet state. 10 : 1000us minimum wait time in Detect.Quiet state. 11 : 2000us minimum wait time in Detect.Quiet state. Signed-off-by: Nadeem Athani <nadeem@cadence.com> --- .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index 293b8ec318bc..a1d56e0be419 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -27,6 +27,18 @@ properties: msi-parent: true + detect-quiet-min-delay: + description: + LTSSM Detect.Quiet state minimum delay. + 00 : 0us minimum wait time + 01 : 100us minimum wait time + 10 : 1000us minimum wait time + 11 : 2000us minimum wait time + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + required: - reg - reg-names @@ -48,6 +60,7 @@ examples: linux,pci-domain = <0>; vendor-id = <0x17cd>; device-id = <0x0200>; + detect-quiet-min-delay = <0>; reg = <0x0 0xfb000000 0x0 0x01000000>, <0x0 0x41000000 0x0 0x00001000>; -- 2.15.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings:pci: Set LTSSM Detect.Quiet state delay. 2021-03-09 7:31 ` [PATCH 1/2] dt-bindings:pci: " Nadeem Athani @ 2021-03-09 16:46 ` Rob Herring 2021-03-14 18:56 ` Athani Nadeem Ladkhan 2021-03-09 17:19 ` Rob Herring 1 sibling, 1 reply; 7+ messages in thread From: Rob Herring @ 2021-03-09 16:46 UTC (permalink / raw) To: Nadeem Athani Cc: Tom Joseph, Bjorn Helgaas, PCI, devicetree, linux-kernel, Lorenzo Pieralisi, Kishon Vijay Abraham I, Milind Parab, Swapnil Kashinath Jakhade, Parshuram Raju Thombare On Tue, Mar 9, 2021 at 12:31 AM Nadeem Athani <nadeem@cadence.com> wrote: > > The parameter detect-quiet-min-delay can be used to program the minimum > time that LTSSM waits on entering Detect.Quiet state. > 00 : 0us minimum wait time in Detect.Quiet state. > 01 : 100us minimum wait time in Detect.Quiet state. > 10 : 1000us minimum wait time in Detect.Quiet state. > 11 : 2000us minimum wait time in Detect.Quiet state. What determines this setting? Is it per board or SoC? Is this a standard PCI timing thing? Why does this need to be tuned per platform? > Signed-off-by: Nadeem Athani <nadeem@cadence.com> > --- > .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > index 293b8ec318bc..a1d56e0be419 100644 > --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > @@ -27,6 +27,18 @@ properties: > > msi-parent: true > > + detect-quiet-min-delay: > + description: > + LTSSM Detect.Quiet state minimum delay. > + 00 : 0us minimum wait time > + 01 : 100us minimum wait time > + 10 : 1000us minimum wait time > + 11 : 2000us minimum wait time > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 3 > + default: 0 > + > required: > - reg > - reg-names > @@ -48,6 +60,7 @@ examples: > linux,pci-domain = <0>; > vendor-id = <0x17cd>; > device-id = <0x0200>; > + detect-quiet-min-delay = <0>; > > reg = <0x0 0xfb000000 0x0 0x01000000>, > <0x0 0x41000000 0x0 0x00001000>; > -- > 2.15.0 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/2] dt-bindings:pci: Set LTSSM Detect.Quiet state delay. 2021-03-09 16:46 ` Rob Herring @ 2021-03-14 18:56 ` Athani Nadeem Ladkhan 0 siblings, 0 replies; 7+ messages in thread From: Athani Nadeem Ladkhan @ 2021-03-14 18:56 UTC (permalink / raw) To: Rob Herring Cc: Tom Joseph, Bjorn Helgaas, PCI, devicetree, linux-kernel, Lorenzo Pieralisi, Kishon Vijay Abraham I, Milind Parab, Swapnil Kashinath Jakhade, Parshuram Raju Thombare Hi Rob, > -----Original Message----- > From: Rob Herring <robh+dt@kernel.org> > Sent: Tuesday, March 9, 2021 10:17 PM > To: Athani Nadeem Ladkhan <nadeem@cadence.com> > Cc: Tom Joseph <tjoseph@cadence.com>; Bjorn Helgaas > <bhelgaas@google.com>; PCI <linux-pci@vger.kernel.org>; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Lorenzo Pieralisi > <lorenzo.pieralisi@arm.com>; Kishon Vijay Abraham I <kishon@ti.com>; > Milind Parab <mparab@cadence.com>; Swapnil Kashinath Jakhade > <sjakhade@cadence.com>; Parshuram Raju Thombare > <pthombar@cadence.com> > Subject: Re: [PATCH 1/2] dt-bindings:pci: Set LTSSM Detect.Quiet state delay. > > EXTERNAL MAIL > > > On Tue, Mar 9, 2021 at 12:31 AM Nadeem Athani <nadeem@cadence.com> > wrote: > > > > The parameter detect-quiet-min-delay can be used to program the > > minimum time that LTSSM waits on entering Detect.Quiet state. > > 00 : 0us minimum wait time in Detect.Quiet state. > > 01 : 100us minimum wait time in Detect.Quiet state. > > 10 : 1000us minimum wait time in Detect.Quiet state. > > 11 : 2000us minimum wait time in Detect.Quiet state. > > What determines this setting? Is it per board or SoC? Is this a standard PCI > timing thing? Why does this need to be tuned per platform? The pcie spec. says this delay to be between 0 to 1ms. The default 0 value works in most cases. However it has been found that some SOC may require this delay to be greater than 0. This has been proved by an internal simulation experiments. Hence providing this feature in device tree for required SOC's. > > > Signed-off-by: Nadeem Athani <nadeem@cadence.com> > > --- > > .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 13 > +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > index 293b8ec318bc..a1d56e0be419 100644 > > --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > @@ -27,6 +27,18 @@ properties: > > > > msi-parent: true > > > > + detect-quiet-min-delay: > > + description: > > + LTSSM Detect.Quiet state minimum delay. > > + 00 : 0us minimum wait time > > + 01 : 100us minimum wait time > > + 10 : 1000us minimum wait time > > + 11 : 2000us minimum wait time > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 0 > > + maximum: 3 > > + default: 0 > > + > > required: > > - reg > > - reg-names > > @@ -48,6 +60,7 @@ examples: > > linux,pci-domain = <0>; > > vendor-id = <0x17cd>; > > device-id = <0x0200>; > > + detect-quiet-min-delay = <0>; > > > > reg = <0x0 0xfb000000 0x0 0x01000000>, > > <0x0 0x41000000 0x0 0x00001000>; > > -- > > 2.15.0 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings:pci: Set LTSSM Detect.Quiet state delay. 2021-03-09 7:31 ` [PATCH 1/2] dt-bindings:pci: " Nadeem Athani 2021-03-09 16:46 ` Rob Herring @ 2021-03-09 17:19 ` Rob Herring 1 sibling, 0 replies; 7+ messages in thread From: Rob Herring @ 2021-03-09 17:19 UTC (permalink / raw) To: Nadeem Athani Cc: mparab, devicetree, tjoseph, sjakhade, bhelgaas, lorenzo.pieralisi, robh+dt, linux-kernel, linux-pci, kishon, pthombar On Tue, 09 Mar 2021 08:31:41 +0100, Nadeem Athani wrote: > The parameter detect-quiet-min-delay can be used to program the minimum > time that LTSSM waits on entering Detect.Quiet state. > 00 : 0us minimum wait time in Detect.Quiet state. > 01 : 100us minimum wait time in Detect.Quiet state. > 10 : 1000us minimum wait time in Detect.Quiet state. > 11 : 2000us minimum wait time in Detect.Quiet state. > > Signed-off-by: Nadeem Athani <nadeem@cadence.com> > --- > .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml:33:10: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml: mapping values are not allowed in this context in "<unicode string>", line 33, column 10 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml: ignoring, error parsing file warning: no schema found in file: ./Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml Traceback (most recent call last): File "/usr/local/bin/dt-extract-example", line 45, in <module> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read()) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load return constructor.get_single_data() File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data node = self.composer.get_single_node() File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 891, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event ruamel.yaml.scanner.ScannerError: mapping values are not allowed in this context in "<unicode string>", line 33, column 10 make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.example.dts] Error 1 make[1]: *** Deleting file 'Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.example.dts' make: *** [Makefile:1380: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1449563 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] PCI: cadence: Set LTSSM Detect.Quiet state delay. 2021-03-09 7:31 [PATCH 0/2] PCI: cadence: Set LTSSM Detect.Quiet state delay Nadeem Athani 2021-03-09 7:31 ` [PATCH 1/2] dt-bindings:pci: " Nadeem Athani @ 2021-03-09 7:31 ` Nadeem Athani 2021-03-15 13:11 ` Kishon Vijay Abraham I 1 sibling, 1 reply; 7+ messages in thread From: Nadeem Athani @ 2021-03-09 7:31 UTC (permalink / raw) To: tjoseph, bhelgaas, robh+dt, linux-pci, devicetree, linux-kernel, lorenzo.pieralisi, robh, kishon Cc: mparab, sjakhade, nadeem, pthombar The parameter detect_quiet_min_delay can be used to program the minimum time that LTSSM waits on entering Detect.Quiet state. 00 : 0us minimum wait time in Detect.Quiet state. 01 : 100us minimum wait time in Detect.Quiet state. 10 : 1000us minimum wait time in Detect.Quiet state. 11 : 2000us minimum wait time in Detect.Quiet state. As per PCIe specification, all Receivers must meet the Z-RX-DC specification for 2.5 GT/s within 1000us of entering Detect.Quiet LTSSM substate. The LTSSM must stay in this substate until the ZRXDC specification for 2.5 GT/s is met. Signed-off-by: Nadeem Athani <nadeem@cadence.com> --- drivers/pci/controller/cadence/pcie-cadence-host.c | 22 ++++++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 10 ++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 73dcf8cf98fb..056161b3fe65 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -461,6 +461,20 @@ static int cdns_pcie_host_init(struct device *dev, return cdns_pcie_host_init_address_translation(rc); } +static void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie = &rc->pcie; + u32 delay = rc->detect_quiet_min_delay; + u32 ltssm_control_cap; + + ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); + ltssm_control_cap = ((ltssm_control_cap & + ~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay)); + + cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); +} + int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; @@ -485,6 +499,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) rc->device_id = 0xffff; of_property_read_u32(np, "device-id", &rc->device_id); + rc->detect_quiet_min_delay = 0; + of_property_read_u32(np, "detect-quiet-min-delay", + &rc->detect_quiet_min_delay); + pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); if (IS_ERR(pcie->reg_base)) { dev_err(dev, "missing \"reg\"\n"); @@ -497,6 +515,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) return PTR_ERR(rc->cfg_base); rc->cfg_res = res; + /* Default Detect.Quiet state delay is 0 */ + if (rc->detect_quiet_min_delay) + cdns_pcie_detect_quiet_min_delay_set(rc); + ret = cdns_pcie_start_link(pcie); if (ret) { dev_err(dev, "Failed to start link\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 254d2570f8c9..f2d3cca2c707 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -189,6 +189,14 @@ /* AXI link down register */ #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) +/* LTSSM Capabilities register */ +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED = -1, RP_BAR0, @@ -289,6 +297,7 @@ struct cdns_pcie { * single function at a time * @vendor_id: PCI vendor ID * @device_id: PCI device ID + * @detect_quiet_min_delay: LTSSM Detect Quite state min. delay * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 @@ -299,6 +308,7 @@ struct cdns_pcie_rc { void __iomem *cfg_base; u32 vendor_id; u32 device_id; + u32 detect_quiet_min_delay; bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; bool quirk_retrain_flag; }; -- 2.15.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] PCI: cadence: Set LTSSM Detect.Quiet state delay. 2021-03-09 7:31 ` [PATCH 2/2] PCI: cadence: " Nadeem Athani @ 2021-03-15 13:11 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 7+ messages in thread From: Kishon Vijay Abraham I @ 2021-03-15 13:11 UTC (permalink / raw) To: Nadeem Athani, tjoseph, bhelgaas, robh+dt, linux-pci, devicetree, linux-kernel, lorenzo.pieralisi, robh Cc: mparab, sjakhade, pthombar Hi Nadeem, On 09/03/21 1:01 pm, Nadeem Athani wrote: > The parameter detect_quiet_min_delay can be used to program the minimum > time that LTSSM waits on entering Detect.Quiet state. > 00 : 0us minimum wait time in Detect.Quiet state. > 01 : 100us minimum wait time in Detect.Quiet state. > 10 : 1000us minimum wait time in Detect.Quiet state. > 11 : 2000us minimum wait time in Detect.Quiet state. > > As per PCIe specification, all Receivers must meet the Z-RX-DC > specification for 2.5 GT/s within 1000us of entering Detect.Quiet LTSSM > substate. The LTSSM must stay in this substate until the ZRXDC > specification for 2.5 GT/s is met. > > Signed-off-by: Nadeem Athani <nadeem@cadence.com> > --- > drivers/pci/controller/cadence/pcie-cadence-host.c | 22 ++++++++++++++++++++++ > drivers/pci/controller/cadence/pcie-cadence.h | 10 ++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c > index 73dcf8cf98fb..056161b3fe65 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c > @@ -461,6 +461,20 @@ static int cdns_pcie_host_init(struct device *dev, > return cdns_pcie_host_init_address_translation(rc); > } > > +static void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie_rc *rc) > +{ > + struct cdns_pcie *pcie = &rc->pcie; > + u32 delay = rc->detect_quiet_min_delay; > + u32 ltssm_control_cap; > + > + ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); > + ltssm_control_cap = ((ltssm_control_cap & > + ~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) | > + CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay)); > + > + cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); > +} > + The issue is not specific to only host mode. Thanks Kishon > int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) > { > struct device *dev = rc->pcie.dev; > @@ -485,6 +499,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) > rc->device_id = 0xffff; > of_property_read_u32(np, "device-id", &rc->device_id); > > + rc->detect_quiet_min_delay = 0; > + of_property_read_u32(np, "detect-quiet-min-delay", > + &rc->detect_quiet_min_delay); > + > pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); > if (IS_ERR(pcie->reg_base)) { > dev_err(dev, "missing \"reg\"\n"); > @@ -497,6 +515,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) > return PTR_ERR(rc->cfg_base); > rc->cfg_res = res; > > + /* Default Detect.Quiet state delay is 0 */ > + if (rc->detect_quiet_min_delay) > + cdns_pcie_detect_quiet_min_delay_set(rc); > + > ret = cdns_pcie_start_link(pcie); > if (ret) { > dev_err(dev, "Failed to start link\n"); > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h > index 254d2570f8c9..f2d3cca2c707 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence.h > +++ b/drivers/pci/controller/cadence/pcie-cadence.h > @@ -189,6 +189,14 @@ > /* AXI link down register */ > #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) > > +/* LTSSM Capabilities register */ > +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) > +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) > +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 > +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ > + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ > + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) > + > enum cdns_pcie_rp_bar { > RP_BAR_UNDEFINED = -1, > RP_BAR0, > @@ -289,6 +297,7 @@ struct cdns_pcie { > * single function at a time > * @vendor_id: PCI vendor ID > * @device_id: PCI device ID > + * @detect_quiet_min_delay: LTSSM Detect Quite state min. delay > * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or > * available > * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 > @@ -299,6 +308,7 @@ struct cdns_pcie_rc { > void __iomem *cfg_base; > u32 vendor_id; > u32 device_id; > + u32 detect_quiet_min_delay; > bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; > bool quirk_retrain_flag; > }; > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-03-15 13:12 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-09 7:31 [PATCH 0/2] PCI: cadence: Set LTSSM Detect.Quiet state delay Nadeem Athani 2021-03-09 7:31 ` [PATCH 1/2] dt-bindings:pci: " Nadeem Athani 2021-03-09 16:46 ` Rob Herring 2021-03-14 18:56 ` Athani Nadeem Ladkhan 2021-03-09 17:19 ` Rob Herring 2021-03-09 7:31 ` [PATCH 2/2] PCI: cadence: " Nadeem Athani 2021-03-15 13:11 ` Kishon Vijay Abraham I
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