From: Rob Herring <robh@kernel.org>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: PCI <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
devicetree@vger.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Michal Simek <michals@xilinx.com>
Subject: Re: [PATCH] dt-bindings: PCI: xilinx-cpm: Change reg property order
Date: Wed, 4 May 2022 10:43:47 -0500 [thread overview]
Message-ID: <CAL_JsqJkHRbXoHdgDYgeF5JhdPgDhjCg=W7YUmCRdBR8xSKz6A@mail.gmail.com> (raw)
In-Reply-To: <20220429130221.32113-1-bharat.kumar.gogada@xilinx.com>
On Fri, Apr 29, 2022 at 8:02 AM Bharat Kumar Gogada
<bharat.kumar.gogada@xilinx.com> wrote:
>
> Describe cpm reg property before cfg reg property to align with
> node name.
The order is an ABI. If breaking it is okay, explain why here.
>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
> .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index 32f4641085bc..cca395317a4c 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -18,13 +18,13 @@ properties:
>
> reg:
> items:
> - - description: Configuration space region and bridge registers.
> - description: CPM system level control and status registers.
> + - description: Configuration space region and bridge registers.
>
> reg-names:
> items:
> - - const: cfg
> - const: cpm_slcr
> + - const: cfg
>
> interrupts:
> maxItems: 1
> @@ -86,9 +86,9 @@ examples:
> ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
> <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
> msi-map = <0x0 &its_gic 0x0 0x10000>;
> - reg = <0x6 0x00000000 0x0 0x10000000>,
> - <0x0 0xfca10000 0x0 0x1000>;
> - reg-names = "cfg", "cpm_slcr";
> + reg = <0x0 0xfca10000 0x0 0x1000>,
> + <0x6 0x00000000 0x0 0x10000000>;
> + reg-names = "cpm_slcr", "cfg";
> pcie_intc_0: interrupt-controller {
> #address-cells = <0>;
> #interrupt-cells = <1>;
> --
> 2.17.1
>
next prev parent reply other threads:[~2022-05-04 15:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 13:02 [PATCH] dt-bindings: PCI: xilinx-cpm: Change reg property order Bharat Kumar Gogada
2022-04-29 13:27 ` Michal Simek
2022-05-04 15:43 ` Rob Herring [this message]
2022-05-10 7:29 ` Michal Simek
2022-05-10 16:00 ` Rob Herring
2022-05-10 17:18 ` Michal Simek
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