From: Rob Herring <robh+dt@kernel.org>
To: srikanth.thokala@intel.com
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
PCI <linux-pci@vger.kernel.org>,
devicetree@vger.kernel.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mark Gross <mgross@linux.intel.com>,
"Raja Subramanian,
Lakshmi Bai" <lakshmi.bai.raja.subramanian@intel.com>,
mallikarjunappa.sangannavar@intel.com,
Krzysztof Wilczynski <kw@linux.com>
Subject: Re: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay
Date: Tue, 15 Jun 2021 15:09:01 -0600 [thread overview]
Message-ID: <CAL_JsqJmLz2TChWYGtEGtHpd5aO4hp+zvx8cExb760PDsx-nRg@mail.gmail.com> (raw)
In-Reply-To: <20210607154044.26074-3-srikanth.thokala@intel.com>
On Mon, Jun 7, 2021 at 1:47 AM <srikanth.thokala@intel.com> wrote:
>
> From: Srikanth Thokala <srikanth.thokala@intel.com>
>
> Add driver for Intel Keem Bay SoC PCIe controller. This controller
> is based on DesignWare PCIe core.
>
> In Root Complex mode, only internal reference clock is possible for
> Keem Bay A0. For Keem Bay B0, external reference clock can be used
> and will be the default configuration. Currently, keembay_pcie_of_data
> structure has one member. It will be expanded later to handle this
> difference.
>
> Endpoint mode link initialization is handled by the boot firmware.
>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com>
> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
> ---
> MAINTAINERS | 7 +
> drivers/pci/controller/dwc/Kconfig | 28 ++
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-keembay.c | 451 ++++++++++++++++++++++
> 4 files changed, 487 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-keembay.c
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2021-06-15 21:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 15:40 [PATCH v10 0/2] PCI: keembay: Add support for Intel Keem Bay srikanth.thokala
2021-06-07 15:40 ` [PATCH v10 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller srikanth.thokala
2021-06-07 15:40 ` [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay srikanth.thokala
2021-06-15 21:09 ` Rob Herring [this message]
2021-06-16 7:49 ` Thokala, Srikanth
2021-06-21 16:53 ` Lorenzo Pieralisi
2021-06-25 3:23 ` Thokala, Srikanth
2021-07-07 11:54 ` Thokala, Srikanth
2021-07-26 6:30 ` Thokala, Srikanth
2021-07-26 8:00 ` Marc Zyngier
2021-07-27 16:26 ` Thokala, Srikanth
2021-06-15 14:38 ` [PATCH v10 0/2] " Thokala, Srikanth
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAL_JsqJmLz2TChWYGtEGtHpd5aO4hp+zvx8cExb760PDsx-nRg@mail.gmail.com \
--to=robh+dt@kernel.org \
--cc=andriy.shevchenko@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=kw@linux.com \
--cc=lakshmi.bai.raja.subramanian@intel.com \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mallikarjunappa.sangannavar@intel.com \
--cc=mgross@linux.intel.com \
--cc=srikanth.thokala@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).