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* [QUESTION]: Same IO bus address in different _CRS methods
@ 2017-03-09 15:41 Gabriele Paoloni
  2017-03-09 18:11 ` Bjorn Helgaas
  0 siblings, 1 reply; 8+ messages in thread
From: Gabriele Paoloni @ 2017-03-09 15:41 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: Tomasz Nowicki, Lorenzo Pieralisi, arnd, agraf, Yuanzhichang,
	xuwei (O),
	John Garry, linux-pci, linux-acpi

Hi Bjorn and all

I have a question regarding bus addresses for IO resources in the ACPI table.

The question is if from an ACPI perspective it is legal to have two entries in
separate _CRS methods using the same IO bus address.

As an example please see the code at the bottom: we have the same bus address
starting at 0x0 with (obviously) different offsets leading to different CPU
physical addresses. Is this legal?

p.s. full DSDT is here:
https://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git/tree/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl?h=estuary-rp

Many thanks
Gab

----

  Device (PCI0)
  {
    Name (_HID, "HISI0080") // PCI Express Root Bridge
    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
    Name(_SEG, 0) // Segment of this Root complex
    Name(_BBN, 0) // Base Bus Number
    Name(_CCA, 1)
    Method (_CRS, 0, Serialized) { // Root complex resources

[...]

        QWordIO (
          ResourceProducer,
          MinFixed,
          MaxFixed,
          PosDecode,
          EntireRange,
          0x0, // Granularity
          0x0, // Min Base Address
          0xffff, // Max Base Address
          0xb7ff0000, // Translate
          0x10000 // Length
        )
      }) // Name(RBUF)
      Return (RBUF)
    } // Method(_CRS)


// PCIe Root bus
  Device (PCI1)
  {
    Name (_HID, "HISI0080") // PCI Express Root Bridge
    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
    Name(_SEG, 1) // Segment of this Root complex
    Name(_BBN, 0xe0) // Base Bus Number
    Name(_CCA, 1)
    Method (_CRS, 0, Serialized) { // Root complex resources

[...]

        QWordIO (
          ResourceProducer,
          MinFixed,
          MaxFixed,
          PosDecode,
          EntireRange,
          0x0, // Granularity
          0x0, // Min Base Address
          0xffff, // Max Base Address
          0xbdff0000, // Translate
          0x10000 // Length
        )
      }) // Name(RBUF)
      Return (RBUF)
    } // Method(_CRS)

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-09 15:41 [QUESTION]: Same IO bus address in different _CRS methods Gabriele Paoloni
@ 2017-03-09 18:11 ` Bjorn Helgaas
  2017-03-09 22:09   ` Arnd Bergmann
  0 siblings, 1 reply; 8+ messages in thread
From: Bjorn Helgaas @ 2017-03-09 18:11 UTC (permalink / raw)
  To: Gabriele Paoloni
  Cc: Bjorn Helgaas, Tomasz Nowicki, Lorenzo Pieralisi, arnd, agraf,
	Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

On Thu, Mar 09, 2017 at 03:41:03PM +0000, Gabriele Paoloni wrote:
> Hi Bjorn and all
> 
> I have a question regarding bus addresses for IO resources in the
> ACPI table.
> 
> The question is if from an ACPI perspective it is legal to have two
> entries in separate _CRS methods using the same IO bus address.
> 
> As an example please see the code at the bottom: we have the same
> bus address starting at 0x0 with (obviously) different offsets
> leading to different CPU physical addresses. Is this legal?

Yes.

These are on separate PCI buses (PCI0 leads to 0000:00 and PCI1 leads
to 0001:e0), so there should be no conflict.  Those are completely
independent PCI buses, and their bus address spaces are also
independent.

You do have to make sure the CPU physical addresses don't conflict, of
course.

It looks like these are memory space on the CPU side, and the bridge
converts it to PCI I/O space, right?  There is an ACPI _TTP bit to
indicate this, which I don't see in your descriptors.

> p.s. full DSDT is here:
> https://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git/tree/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl?h=estuary-rp
> 
> Many thanks
> Gab
> 
> ----
> 
>   Device (PCI0)
>   {
>     Name (_HID, "HISI0080") // PCI Express Root Bridge
>     Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
>     Name(_SEG, 0) // Segment of this Root complex
>     Name(_BBN, 0) // Base Bus Number
>     Name(_CCA, 1)
>     Method (_CRS, 0, Serialized) { // Root complex resources
> 
> [...]
> 
>         QWordIO (
>           ResourceProducer,
>           MinFixed,
>           MaxFixed,
>           PosDecode,
>           EntireRange,
>           0x0, // Granularity
>           0x0, // Min Base Address
>           0xffff, // Max Base Address
>           0xb7ff0000, // Translate
>           0x10000 // Length
>         )
>       }) // Name(RBUF)
>       Return (RBUF)
>     } // Method(_CRS)
> 
> 
> // PCIe Root bus
>   Device (PCI1)
>   {
>     Name (_HID, "HISI0080") // PCI Express Root Bridge
>     Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
>     Name(_SEG, 1) // Segment of this Root complex
>     Name(_BBN, 0xe0) // Base Bus Number
>     Name(_CCA, 1)
>     Method (_CRS, 0, Serialized) { // Root complex resources
> 
> [...]
> 
>         QWordIO (
>           ResourceProducer,
>           MinFixed,
>           MaxFixed,
>           PosDecode,
>           EntireRange,
>           0x0, // Granularity
>           0x0, // Min Base Address
>           0xffff, // Max Base Address
>           0xbdff0000, // Translate
>           0x10000 // Length
>         )
>       }) // Name(RBUF)
>       Return (RBUF)
>     } // Method(_CRS)
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-09 18:11 ` Bjorn Helgaas
@ 2017-03-09 22:09   ` Arnd Bergmann
  2017-03-09 22:37     ` Bjorn Helgaas
  0 siblings, 1 reply; 8+ messages in thread
From: Arnd Bergmann @ 2017-03-09 22:09 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: Gabriele Paoloni, Bjorn Helgaas, Tomasz Nowicki,
	Lorenzo Pieralisi, agraf, Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

On Thu, Mar 9, 2017 at 7:11 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Thu, Mar 09, 2017 at 03:41:03PM +0000, Gabriele Paoloni wrote:
>> Hi Bjorn and all
>>
>> I have a question regarding bus addresses for IO resources in the
>> ACPI table.
>>
>> The question is if from an ACPI perspective it is legal to have two
>> entries in separate _CRS methods using the same IO bus address.
>>
>> As an example please see the code at the bottom: we have the same
>> bus address starting at 0x0 with (obviously) different offsets
>> leading to different CPU physical addresses. Is this legal?
>
> Yes.
>
> These are on separate PCI buses (PCI0 leads to 0000:00 and PCI1 leads
> to 0001:e0), so there should be no conflict.  Those are completely
> independent PCI buses, and their bus address spaces are also
> independent.
>
> You do have to make sure the CPU physical addresses don't conflict, of
> course.

Ok. My reading of the ia64 code was that it would reject this as being
overlapping resources, but I was probably misreading then.

What is the expected way to deal with a device using an I/O resource
that is not a child of either PCI host bridge in this case (e.g. a
BMC behind a PCI-LPC bridge)? Is this only allowed to exist below
the device that provides the respective I/O space?

     Arnd

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-09 22:09   ` Arnd Bergmann
@ 2017-03-09 22:37     ` Bjorn Helgaas
  2017-03-09 22:50       ` Arnd Bergmann
  0 siblings, 1 reply; 8+ messages in thread
From: Bjorn Helgaas @ 2017-03-09 22:37 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Gabriele Paoloni, Bjorn Helgaas, Tomasz Nowicki,
	Lorenzo Pieralisi, agraf, Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

On Thu, Mar 09, 2017 at 11:09:24PM +0100, Arnd Bergmann wrote:
> On Thu, Mar 9, 2017 at 7:11 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Thu, Mar 09, 2017 at 03:41:03PM +0000, Gabriele Paoloni wrote:
> >> Hi Bjorn and all
> >>
> >> I have a question regarding bus addresses for IO resources in the
> >> ACPI table.
> >>
> >> The question is if from an ACPI perspective it is legal to have two
> >> entries in separate _CRS methods using the same IO bus address.
> >>
> >> As an example please see the code at the bottom: we have the same
> >> bus address starting at 0x0 with (obviously) different offsets
> >> leading to different CPU physical addresses. Is this legal?
> >
> > Yes.
> >
> > These are on separate PCI buses (PCI0 leads to 0000:00 and PCI1 leads
> > to 0001:e0), so there should be no conflict.  Those are completely
> > independent PCI buses, and their bus address spaces are also
> > independent.
> >
> > You do have to make sure the CPU physical addresses don't conflict, of
> > course.
> 
> Ok. My reading of the ia64 code was that it would reject this as being
> overlapping resources, but I was probably misreading then.

I'm fairly sure ia64 supported multiple 0-0xffff I/O port spaces (in PCI
I/O space), but I don't have dmesg logs from any of those machines any
more.

> What is the expected way to deal with a device using an I/O resource
> that is not a child of either PCI host bridge in this case (e.g. a
> BMC behind a PCI-LPC bridge)? Is this only allowed to exist below
> the device that provides the respective I/O space?

That's a good question.  I'm not really familiar with PCI-LPC bridges.
I guess they're not PCI-to-PCI bridges and wouldn't have I/O windows
like I'm used to?  What *do* they look like?

Bjorn

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-09 22:37     ` Bjorn Helgaas
@ 2017-03-09 22:50       ` Arnd Bergmann
  2017-03-10  0:25         ` Gabriele Paoloni
  0 siblings, 1 reply; 8+ messages in thread
From: Arnd Bergmann @ 2017-03-09 22:50 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: Gabriele Paoloni, Bjorn Helgaas, Tomasz Nowicki,
	Lorenzo Pieralisi, agraf, Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

On Thu, Mar 9, 2017 at 11:37 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Thu, Mar 09, 2017 at 11:09:24PM +0100, Arnd Bergmann wrote:
>> On Thu, Mar 9, 2017 at 7:11 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
>> > On Thu, Mar 09, 2017 at 03:41:03PM +0000, Gabriele Paoloni wrote:
>> >> Hi Bjorn and all
>> >>
>> >> I have a question regarding bus addresses for IO resources in the
>> >> ACPI table.
>> >>
>> >> The question is if from an ACPI perspective it is legal to have two
>> >> entries in separate _CRS methods using the same IO bus address.
>> >>
>> >> As an example please see the code at the bottom: we have the same
>> >> bus address starting at 0x0 with (obviously) different offsets
>> >> leading to different CPU physical addresses. Is this legal?
>> >
>> > Yes.
>> >
>> > These are on separate PCI buses (PCI0 leads to 0000:00 and PCI1 leads
>> > to 0001:e0), so there should be no conflict.  Those are completely
>> > independent PCI buses, and their bus address spaces are also
>> > independent.
>> >
>> > You do have to make sure the CPU physical addresses don't conflict, of
>> > course.
>>
>> Ok. My reading of the ia64 code was that it would reject this as being
>> overlapping resources, but I was probably misreading then.
>
> I'm fairly sure ia64 supported multiple 0-0xffff I/O port spaces (in PCI
> I/O space), but I don't have dmesg logs from any of those machines any
> more.

Ok. I've read the code again and you are right: ia64 checks that the
CPU address is unique, not the PCI I/O space address.

>> What is the expected way to deal with a device using an I/O resource
>> that is not a child of either PCI host bridge in this case (e.g. a
>> BMC behind a PCI-LPC bridge)? Is this only allowed to exist below
>> the device that provides the respective I/O space?
>
> That's a good question.  I'm not really familiar with PCI-LPC bridges.
> I guess they're not PCI-to-PCI bridges and wouldn't have I/O windows
> like I'm used to?  What *do* they look like?

They are like PCI-ISA bridges, connecting devices that use either
hardcoded I/O ports (uart, ipmi-kcs, ...) or ISAPNP.

In the case that we are interested in specifically here, there is not
actually a PCI-LPC bridge, but a LPC host bridge that is independent
of PCI but has its own I/O space, and a number of child devices attached
to that.

      Arnd

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-09 22:50       ` Arnd Bergmann
@ 2017-03-10  0:25         ` Gabriele Paoloni
  2017-03-10  7:45           ` Arnd Bergmann
  0 siblings, 1 reply; 8+ messages in thread
From: Gabriele Paoloni @ 2017-03-10  0:25 UTC (permalink / raw)
  To: Arnd Bergmann, Bjorn Helgaas
  Cc: Bjorn Helgaas, Tomasz Nowicki, Lorenzo Pieralisi, agraf,
	Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

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^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-10  0:25         ` Gabriele Paoloni
@ 2017-03-10  7:45           ` Arnd Bergmann
  2017-03-10  9:57             ` Gabriele Paoloni
  0 siblings, 1 reply; 8+ messages in thread
From: Arnd Bergmann @ 2017-03-10  7:45 UTC (permalink / raw)
  To: Gabriele Paoloni
  Cc: Bjorn Helgaas, Bjorn Helgaas, Tomasz Nowicki, Lorenzo Pieralisi,
	agraf, Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

On Fri, Mar 10, 2017 at 1:25 AM, Gabriele Paoloni
<gabriele.paoloni@huawei.com> wrote:
>> -----Original Message-----
>> From: arndbergmann@gmail.com [mailto:arndbergmann@gmail.com] On Behalf
>> Of Arnd Bergmann
>> Sent: 09 March 2017 22:50
>> To: Bjorn Helgaas
>> Cc: Gabriele Paoloni; Bjorn Helgaas; Tomasz Nowicki; Lorenzo Pieralisi;
>> agraf@suse.de; Yuanzhichang; xuwei (O); John Garry; linux-
>> pci@vger.kernel.org; linux-acpi@vger.kernel.org
>> Subject: Re: [QUESTION]: Same IO bus address in different _CRS methods
>> >> What is the expected way to deal with a device using an I/O resource
>> >> that is not a child of either PCI host bridge in this case (e.g. a
>> >> BMC behind a PCI-LPC bridge)? Is this only allowed to exist below
>> >> the device that provides the respective I/O space?
>> >
>> > That's a good question.  I'm not really familiar with PCI-LPC
>> bridges.
>> > I guess they're not PCI-to-PCI bridges and wouldn't have I/O windows
>> > like I'm used to?  What *do* they look like?
>>
>> They are like PCI-ISA bridges, connecting devices that use either
>> hardcoded I/O ports (uart, ipmi-kcs, ...) or ISAPNP.
>>
>> In the case that we are interested in specifically here, there is not
>> actually a PCI-LPC bridge, but a LPC host bridge that is independent
>> of PCI but has its own I/O space, and a number of child devices
>> attached
>> to that.
>
> I think that for the case that we were discussing we needed to know
> whether we could make the assumption to have unique IO bus addresses
> in a whole ACPI table.
>
> The idea for ACPI was to rework acpi_pci_root_remap_iospace and,
> rather than using the PIO tokens retrieved by pci_register_io_range(),
> remove the call to this function and use the bus addresses defined
> in the _CRS method.
>
> From what Bjorn said it seems that we have at least some cases where
> these bus addresses are not unique; therefore in linux we need to generate
> the PIO tokens dynamically.
>
> If you guys agree on the conclusion above I will continue with the
> rework of the HiSilicon LPC driver with the assumption that we need
> dynamically assigned tokens also for ACPI.

Yes, unless Bjorn has some last concerns, I think this is all good
and the only proper way to continue. Thanks for bearing with me
through the detour that ended up in the same place we were in
before...

    Arnd

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [QUESTION]: Same IO bus address in different _CRS methods
  2017-03-10  7:45           ` Arnd Bergmann
@ 2017-03-10  9:57             ` Gabriele Paoloni
  0 siblings, 0 replies; 8+ messages in thread
From: Gabriele Paoloni @ 2017-03-10  9:57 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Bjorn Helgaas, Bjorn Helgaas, Tomasz Nowicki, Lorenzo Pieralisi,
	agraf, Yuanzhichang, xuwei (O),
	John Garry, linux-pci, linux-acpi

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^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2017-03-10  9:57 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-09 15:41 [QUESTION]: Same IO bus address in different _CRS methods Gabriele Paoloni
2017-03-09 18:11 ` Bjorn Helgaas
2017-03-09 22:09   ` Arnd Bergmann
2017-03-09 22:37     ` Bjorn Helgaas
2017-03-09 22:50       ` Arnd Bergmann
2017-03-10  0:25         ` Gabriele Paoloni
2017-03-10  7:45           ` Arnd Bergmann
2017-03-10  9:57             ` Gabriele Paoloni

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